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[VHDL/FPGA/Verilog] verilog_niuke

牛客网刷题记录,
Niuke.com question brushing record, (2023-08-19, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1692452581746852.html

[VHDL/FPGA/Verilog] half_clk

verilog语言半加器全加器好好看看吧希望对大家有用
Verilog language, half adder, full adder. Have a look. I hope it will be useful to you. (2019-10-28, Verilog, 24KB, 下载0次)

http://www.pudn.com/Download/item/id/1572245146274711.html

[VHDL/FPGA/Verilog] liyuanlnx_key_beep

FPGA按键加蜂鸣器实验：加延时防抖+蜂鸣器
Experiments of keys and buzzers in FPGA (2019-07-24, Quartus II, 379KB, 下载2次)

http://www.pudn.com/Download/item/id/1563950404999685.html

[VHDL/FPGA/Verilog] H_adder

半加器实现，简单的半加器，作为新手实验用
Semi-adder implementation, simple semi-adder, as a novice experiment (2019-06-12, Verilog, 2960KB, 下载6次)

http://www.pudn.com/Download/item/id/1560341657785924.html

[VHDL/FPGA/Verilog] Chapter02

实现了4位半加器的verilog HDL代码
Implementation of Verilog code for 4-bit semi-adde (2019-06-10, Verilog, 252KB, 下载0次)

http://www.pudn.com/Download/item/id/1560175914437102.html

[VHDL/FPGA/Verilog] aes

aes加解密算法源代码及testbench平台
AES source code and testbench (2018-06-08, Verilog, 84KB, 下载2次)

http://www.pudn.com/Download/item/id/1528444104183299.html

[VHDL/FPGA/Verilog] EDAadd

全加器Full adder schematic waveform diagram
Full adder schematic waveform diagram (2017-10-13, Quartus II, 2902KB, 下载1次)

http://www.pudn.com/Download/item/id/1507899125521770.html

[VHDL/FPGA/Verilog] OpenM8_CE

大航海脚本美术8脚本,本脚本,已测试只对国服有效
GOV online sc (2016-02-27, C++, 9KB, 下载1次)

http://www.pudn.com/Download/item/id/1456583991841524.html

[VHDL/FPGA/Verilog] half_adder

半加器的VHDL实现，包括Testbench的编写，可供新手参考
Half Adder VHDL Testbench (2015-02-04, VHDL, 964KB, 下载6次)

http://www.pudn.com/Download/item/id/1423043278302843.html

[VHDL/FPGA/Verilog] h_adder

ise13.2环境下VHDL编写的半加器器+仿真波形
ise13.2 environment half adder in VHDL simulation waveform control+ (2013-06-01, Visual C++, 445KB, 下载2次)

http://www.pudn.com/Download/item/id/2266389.html

[VHDL/FPGA/Verilog] h_adder

半加器VHDL代码，包含所有文件，较清晰
Half adder VHDL code, including all documents, clearer (2013-05-17, VHDL, 107KB, 下载3次)

http://www.pudn.com/Download/item/id/2247564.html

[VHDL/FPGA/Verilog] AES__veriloghdl

RAS加解密模块，实现ras加密，解密功能。包括顶层文件，verilog代码实现
RAS Encryption and decryption (2013-04-15, VHDL, 19KB, 下载17次)

http://www.pudn.com/Download/item/id/2201472.html

[VHDL/FPGA/Verilog] full_adder

全加法器，全加器描述，由两个半加器连接而成
full adder (2012-11-09, VHDL, 1KB, 下载4次)

http://www.pudn.com/Download/item/id/2041932.html

[VHDL/FPGA/Verilog] adder

涉及半加器与全加器的电路连线图模块。非语言编写。
FPGA-verilog,full_adder and half_adder. (2011-12-15, VHDL, 199KB, 下载2次)

http://www.pudn.com/Download/item/id/1732414.html

[VHDL/FPGA/Verilog] h_adder

半加器的实现，利用VHDL语言实现半加器的运算
Half adder implementation using VHDL language and a half-adder operation (2011-12-13, VHDL, 40KB, 下载3次)

http://www.pudn.com/Download/item/id/1729472.html

[VHDL/FPGA/Verilog] VHDL

译码器。半加器，全加器。。。包括源程序和仿真波形
Decoder. Half adder, full adder. . . Including the source and the simulation waveform (2010-10-23, VHDL, 341KB, 下载9次)

http://www.pudn.com/Download/item/id/1325271.html

[VHDL/FPGA/Verilog] music_yetong1

电子琴加音乐播放功能，电子琴加音乐播放功能，电子琴加音乐播放功能，电子琴加音乐播放功能，
music play (2010-06-17, VHDL, 485KB, 下载7次)

http://www.pudn.com/Download/item/id/1215642.html

[VHDL/FPGA/Verilog] EDA

课程实验，VHDL语言实现半加器全加器，频率计等，共四个
eda (2010-01-14, VHDL, 2328KB, 下载12次)

http://www.pudn.com/Download/item/id/1040505.html

[VHDL/FPGA/Verilog] multi4

fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器
fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier (2007-02-28, Others, 1KB, 下载23次)

http://www.pudn.com/Download/item/id/251301.html

[VHDL/FPGA/Verilog] VHDL大作业－虞益挺036100486

全加器的VHDL程序实现及仿真
full adder VHDL simulation program and (2005-01-13, C/C++, 86KB, 下载25次)

http://www.pudn.com/Download/item/id/1105593356485726.html