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[VHDL/FPGA/Verilog] Programs-VHDL

[https:www.youtube.com watch v=FzsPFgjVV7Q&ab_channel=FarFromAlaska-主题]（https:www.youtube.com watch v=FzspfgjV57Q&ab_channel=FarFrom阿拉斯加-主题），
[https: www.youtube.com watch v=FzsPFgjVV7Q&ab_channel=FarFromAlaska- Topic](https: www.youtube.com watch v=FzsPFgjVV7Q&ab_channel=FarFromAlaska- Topic), (2023-09-23, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1695621310958636.html

[VHDL/FPGA/Verilog] 一位全加器的设计

全加器等等传输管简易模型，用于传输管的异或运算出来得全加器
A simple model of full adder and other transfer tubes (2018-11-15, Others, 425KB, 下载0次)

http://www.pudn.com/Download/item/id/1542290374284792.html

[VHDL/FPGA/Verilog] quanjiaqi-verilog

基于verilog语言的编写的全加器，基于verilog语言的编写的全加器
quanjiaqi (2015-08-30, VHDL, 1KB, 下载1次)

http://www.pudn.com/Download/item/id/1440903947726983.html

[VHDL/FPGA/Verilog] AES

AES代码加解密代码 systemverilog编程
AES code (2015-01-06, VHDL, 991KB, 下载7次)

http://www.pudn.com/Download/item/id/1420520650553215.html

[VHDL/FPGA/Verilog] add_verilog

2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过
Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output (2014-05-14, VHDL, 1KB, 下载4次)

http://www.pudn.com/Download/item/id/2540756.html

[VHDL/FPGA/Verilog] OFDM

OFDM完美出图，信噪比，16QAM星座图，加窗信号时域和频域波形图
Perfect figure, OFDM SNR, 16 qam constellation diagram, add window signal time domain and frequency domain waveform figure (2013-06-05, matlab, 4KB, 下载143次)

http://www.pudn.com/Download/item/id/2270895.html

[VHDL/FPGA/Verilog] fadder

全加器，由2个半加器构成的VHDL语言，有进位位。
failed to translate (2013-05-07, VHDL, 19KB, 下载3次)

http://www.pudn.com/Download/item/id/2233253.html

[VHDL/FPGA/Verilog] 13234

曼彻斯特编解码曼彻斯特编解码 (2013-01-17, VHDL, 195KB, 下载13次)

http://www.pudn.com/Download/item/id/2120126.html

[VHDL/FPGA/Verilog] full_a4

4位全加器的verilog程序设计.......
Four full adder verilog programming ... (2012-08-13, VHDL, 4158KB, 下载3次)

http://www.pudn.com/Download/item/id/1964538.html

[VHDL/FPGA/Verilog] add

16位的加法器，全加器，有效的利用了门电路用以实现全加器的进位
16 of the adder, full adder and effective use of the gate for the binary full adder (2012-07-12, VHDL, 1KB, 下载4次)

http://www.pudn.com/Download/item/id/1936292.html

[VHDL/FPGA/Verilog] 7483and7485

4位全加器7483和4位比较器7485实现一位8421BCD码全加器
Four full adder 7483, and four comparator 7485 a 8421BCD code full adder (2012-04-29, VHDL, 197KB, 下载13次)

http://www.pudn.com/Download/item/id/1848922.html

[VHDL/FPGA/Verilog] adder4

8421BCD码全加器,这个是最简单的8421加法器，也是最基础的，初学者用来练习
adders for 8241BCD (2011-12-20, VHDL, 306KB, 下载4次)

http://www.pudn.com/Download/item/id/1736803.html

[VHDL/FPGA/Verilog] jiafaqi.rar

数字系统设计及VHDL实践半加器与全加器源代码
half-adder and full-adder (2011-12-10, VHDL, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1726682.html

[VHDL/FPGA/Verilog] avs_aes_latest[1].tar

数字加解密模块的设计
Digital encryption and decryption module design (2011-11-28, VHDL, 408KB, 下载3次)

http://www.pudn.com/Download/item/id/1713744.html

[VHDL/FPGA/Verilog] full_add

全加器，基于原理图设计的全加器。经过时序仿真验证
Full adder, based on the schematic design of the full adder. After timing simulation (2011-06-03, VHDL, 8KB, 下载5次)

http://www.pudn.com/Download/item/id/1558279.html

[VHDL/FPGA/Verilog] example3

加/减法计数器：本程序实现的是一个加/减8进制计数器
Add/down counter: The program implementation is a plus/minus 8 binary counter (2011-03-11, VHDL, 26KB, 下载4次)

http://www.pudn.com/Download/item/id/1451567.html

[VHDL/FPGA/Verilog] ghjk

十进制加法器示范的的游侠的序号的的剑客骄傲到家了库文件发动机阿拉斯加法律
Decimal adder demonstration of the Ranger of the serial number of the swordsman proud home of the library file engine Alaska law (2009-12-14, VHDL, 2KB, 下载7次)

http://www.pudn.com/Download/item/id/1004541.html

[VHDL/FPGA/Verilog] f_adder8

fpga八位全加器(vhdl语言),由画图法制作,将八个一位全加器(由一位半加器组成)组合制成
fpga eight full adder (vhdl language) (2009-08-13, VHDL, 269KB, 下载8次)

http://www.pudn.com/Download/item/id/876551.html

[VHDL/FPGA/Verilog] VHDL03

全加器仿真程序代码，本人亲自测试，代码简单，安全无毒。放心下载和使用。
Full adder simulation code, I personally tested the code simple, safe non-toxic. Ease to download and use. (2009-05-26, VHDL, 1KB, 下载43次)

http://www.pudn.com/Download/item/id/779333.html

[VHDL/FPGA/Verilog] FullAdder_4

这是一个4位全加器，用一个1位半价做的一位全加，然后做成的四位半加。
This is a 4-bit full adder, a half-price with a make a full-adder, and then made four half adder. (2008-03-24, VHDL, 95KB, 下载129次)

http://www.pudn.com/Download/item/id/422084.html