半加器,简单实用,工程,能够使用,初学者以为半加器半加器,简单实用,工程,能够使用,初学者以为半加器
Semi-adder, simple and practical, engineering, can be used, beginners think half-adder and half-adder, simple and practical, engineering, can be used, beginners think half-adder (2018-11-16, VHDL, 293KB, 下载0次)
基于vhdl的八位全加器设计及仿真 包含半加器,一位全加器等基本单元
The design and Simulation of the eight bit full adder based on VHDL include half adder, full adder and other basic units (2018-09-05, VHDL, 3025KB, 下载0次)
编写一位全加器的程序,生成器件后用BLOCK画出bdf图,最终成为四位全加器。此为实验报告,里面包括原理及框图及源程序。
Preparation of a full adder program, after generating device using BLOCK draw bdf map, eventually become four full adders. This is a test report, which includes the principle and block diagram and source code. (2016-01-20, VHDL, 235KB, 下载3次)
之前上传的是全加器,这个是自己设计的8位全加器,8位并行全加器
Before uploading the full adder, this is their own design eight full adders, eight parallel full adder (2015-02-07, VHDL, 256KB, 下载1次)
半加器到全加器,8421码到geleima转换。
Half adder to full adder, 8421 yards to geleima conversion. (2013-11-24, VHDL, 182KB, 下载1次)
32位全加器 使用verilog写的硬件描述语言,xilinx芯片上运行过
32bits full adder (2013-01-27, VHDL, 1KB, 下载7次)
通过调用一位全加器模块,实现四位全加器功能
By calling a full adder module, four full adder function (2012-12-29, VHDL, 1KB, 下载2次)
基于FPGA的半加器,完整工程及代码,已测试
FPGA-based half-adder, full engineering and code (2012-07-11, VHDL, 124KB, 下载3次)
4位全加器和计数器的verilog的例程,还有四位全加器的仿真程序。
Four QuanJia device and counter verilog of the routines, and four QuanJia device simulation program. (2012-03-06, VHDL, 3KB, 下载5次)
由数字电路知识可知,一位全加器可由两个一位半加器与一个或门构成,其原理图如图1所示。该设计利用层次结构描述法,首先设计半加器电路,将其打包为半加器模块;然后在顶层调用半加器模块组成全加器电路;最后将全加器电路编译下载到实验箱,其中ain,bin,cin信号可采用实验箱上SW0,SW1,SW2键作为输入,并将输入的信号连接到红色LED管LEDR0,LEDR1,LEDR2上便于观察,sum,cout信号采用绿色发光二极管LEDG0,LEDG1来显示。
图1.1 全加器原理图
it s a protel (2011-12-17, VHDL, 2KB, 下载3次)
vhdl一位全加器由两个半加器和一个或门组成
This is a vhdl of udcnt4 (2011-12-06, VHDL, 272KB, 下载4次)
VHDL原程序包括译码器,半加器,全加器
VHDL program, including the original decoder, the half adder, full adder (2010-10-23, VHDL, 342KB, 下载11次)
布斯算法 2000
布斯算法 2000
布斯算法 2000
布斯算法 2000
布斯算法 2000
Booth 2000 Booth algorithm algorithm algorithm 2000 Booth 2000 Booth 2000 Booth algorithm algorithm 2000 (2010-05-11, VHDL, 1KB, 下载3次)
vhdl半加半减及全加器的实现即功能具体代码的编写
vhdl half-Canadian half-and full-adder function of the realization that the preparation of a specific code (2009-11-16, VHDL, 1KB, 下载3次)
曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档
Manchester Encoder-Decoder (2009-10-15, VHDL, 40KB, 下载171次)
一位全加器可由两个一位半加器与一个或门构成,该设计利用层次结构描述法,首先设计半加器电路,将其打包为半加器模块;然后在顶层调用半加器模块组成全加器电路
A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical description method, first of all the design half-adder circuit, be packaged as a half-adder module and then call at the top half-adder composed of full-adder circuit modules (2009-10-08, VHDL, 154KB, 下载22次)
全加器结构描述是从设计实体的内部结构对结构体进行描述的,并给出该实体所包含的模块或元件的相互连接关系
fulladd (2009-09-08, VHDL, 204KB, 下载7次)
这是一个8位全加器,利用vhdl完成了电路的构成,
this is a 8 bit adder, (2009-04-27, VHDL, 155KB, 下载2次)
全加器,用fpga语言编写的,可实现数字电路技术中的全加器的功能,符合逻辑原理图。
adder (2009-04-27, VHDL, 3KB, 下载4次)
通过VHDL实现4位全加器,8位全加器,和8位通用寄存器的设计
4-bit full adder
8-bit full adder
8-bit register
using vhdl (2009-02-06, VHDL, 903KB, 下载10次)