维罗格，，
VERILOG,, (2023-08-12, Others, 0KB, 下载0次)
利用Verilog语言编写的，在vivado环境下带进位标志的全加器的工程文件与Testbench
Engineering files and Testbench of the full adder with the carry mark in vivado environment written by Verilog language (2018-08-06, Verilog, 258KB, 下载3次)
通过连续调用半加器组成一位全加器，再次调用一位全加器组成4位全加器。对初学者有一定的指导作用。
Through the continuous call half adder of a full adder, called again of a full adder four full adder. For beginners have a certain guiding role. (2018-05-28, Verilog, 1975KB, 下载0次)
移位加乘法器的实现；移位加乘法器的流水线结构的实现。代码清晰明了。
multiply verilog RTL；pipelin multiply verilog RTL；good coding stytle (2015-09-12, VHDL, 2KB, 下载1次)
之前上传的是全加器，这个是自己设计的8位全加器，8位并行全加器
Before uploading the full adder, this is their own design eight full adders, eight parallel full adder (2015-02-07, VHDL, 256KB, 下载1次)
AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。
AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification. (2014-03-22, Windows_Unix, 16KB, 下载14次)
科斯塔斯环环路滤波器的VHDL实现，仅工参考
VHDL Implementation of Costas Loop the loop filter, the only work of reference
(2012-07-20, matlab, 1KB, 下载26次)
在Quartus II中用VHDL语言编写的全加器与半加器程序，全加器是调用半加器来实现的。
In the Quartus II VHDL language using the full adder and half adder program, full-adder is called a half adder to achieve. (2011-07-03, VHDL, 180KB, 下载4次)
一位全加器,使用绘图方式,将2个半加器制成符号,供全加器调用,组合成全加器,方法简单易行,通过验证.
A full adder, using the drawing method will be made of two half adder symbol calls for the full adder, adder combination of sake, the method is simple and verified. (2010-10-18, VHDL, 184KB, 下载4次)
模拟了半加器和全加器的vhdl语言源码。
model half add and full add mechine vhdl code (2010-06-09, VHDL, 505KB, 下载7次)
曼彻斯特编码器与译码器 FPGA嵌入式项目开发
mancodec fpga (2009-12-23, VHDL, 182KB, 下载127次)
应用一位全加器的VHDL语言，创建一位全加器符号，用原理图完成四位全加器
Application of a full adder VHDL language, to create a full-adder symbol, with the principle of the completion of four full adder diagram (2009-11-29, VHDL, 146KB, 下载15次)
vhdl半加半减及全加器的实现即功能具体代码的编写
vhdl half-Canadian half-and full-adder function of the realization that the preparation of a specific code (2009-11-16, VHDL, 1KB, 下载3次)
全加器结构描述是从设计实体的内部结构对结构体进行描述的，并给出该实体所包含的模块或元件的相互连接关系
fulladd (2009-09-08, VHDL, 204KB, 下载7次)
利用两个半加器来组成的全加器，是简单的vhdl语言入门
The use of two and a half adder to form the full adder is a simple entry-vhdl language (2009-04-09, VHDL, 1KB, 下载4次)
曼彻斯特编码源代码 基于VHDL语言的曼彻斯特编码程序
manchester encode (2009-03-04, VHDL, 1KB, 下载10次)
通过VHDL实现4位全加器，8位全加器，和8位通用寄存器的设计
4-bit full adder
8-bit full adder
8-bit register
using vhdl (2009-02-06, VHDL, 903KB, 下载10次)
自编自写的ＶＨＤＬ代码，用于实现全加器功能，可能有误
, Directed and written in VHDL code, for the realization of full-adder function, may have mistaken (2007-12-24, Others, 4KB, 下载4次)
全加器的VHDL_CODE和TEST_BENCH
無須解壓縮密碼
full adder and the VHDL_CODE TEST_BENCH not extract passwords (2006-04-06, MultiPlatform, 1KB, 下载6次)
曼彻斯特编解码 Xilinx提供的VHDL的源代码
Manchester codec Xilinx provide VHDL source code (2005-10-24, MultiPlatform, 10KB, 下载108次)