维加斯16687406569客服下载搜索联合开发网

[VHDL/FPGA/Verilog] full adder

vhdl实现全加器，vhdl入门学习，vhdl简单程序
Implementation of full adder with VHDL (2021-04-08, Quartus II, 2740KB, 下载0次)

http://www.pudn.com/Download/item/id/1617863946927858.html

[VHDL/FPGA/Verilog] 2_quanjiaqi

1. 利用一位半加器设计八位全加器 2. 进行功能仿真
1. Design of an eight-bit full adder by using a one-and-a-half adder 2. Functional simulation (2019-03-22, Verilog, 678KB, 下载0次)

http://www.pudn.com/Download/item/id/1553268495763442.html

[VHDL/FPGA/Verilog] quanjiaqi2

四位全加器，分模块，分层次设计而成，首先定义全加器顶层模块，然后定义1位全加器，最后定义底层半加器
Four-digit full Adder, divided into modules, and layered design. First define the full Adder top layer module, then define the 1-bit full Adder, and finally define the bottom half Adder. (2018-05-06, C/C++, 987KB, 下载0次)

http://www.pudn.com/Download/item/id/1525587580242827.html

[VHDL/FPGA/Verilog] costas

matlab科斯塔斯环的仿真，有波形，很实用的程序
matlab costas m programm (2017-06-17, matlab, 1KB, 下载15次)

http://www.pudn.com/Download/item/id/1497661691903161.html

[VHDL/FPGA/Verilog] FULL_ADD

编写一位全加器的程序，生成器件后用BLOCK画出bdf图，最终成为四位全加器。此为实验报告，里面包括原理及框图及源程序。
Preparation of a full adder program, after generating device using BLOCK draw bdf map, eventually become four full adders. This is a test report, which includes the principle and block diagram and source code. (2016-01-20, VHDL, 235KB, 下载3次)

http://www.pudn.com/Download/item/id/1453282026233944.html

[VHDL/FPGA/Verilog] M_M

此为数学形态滤波器消燥的代码，用于一维信号，涉及一个具体的例子，需要的话可以自己修改，修改相应的结构元素。
This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements (2013-08-29, matlab, 1KB, 下载104次)

http://www.pudn.com/Download/item/id/2342704.html

[VHDL/FPGA/Verilog] code

32位全加器使用verilog写的硬件描述语言，xilinx芯片上运行过
32bits full adder (2013-01-27, VHDL, 1KB, 下载7次)

http://www.pudn.com/Download/item/id/2128097.html

[VHDL/FPGA/Verilog] bjq

基于FPGA的半加器，完整工程及代码，已测试
FPGA-based half-adder, full engineering and code (2012-07-11, VHDL, 124KB, 下载3次)

http://www.pudn.com/Download/item/id/1935656.html

[VHDL/FPGA/Verilog] Four-adder-and-four--counter

4位全加器和计数器的verilog的例程，还有四位全加器的仿真程序。
Four QuanJia device and counter verilog of the routines, and four QuanJia device simulation program. (2012-03-06, VHDL, 3KB, 下载5次)

http://www.pudn.com/Download/item/id/1786701.html

[VHDL/FPGA/Verilog] fulladder

由数字电路知识可知，一位全加器可由两个一位半加器与一个或门构成，其原理图如图1所示。该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路；最后将全加器电路编译下载到实验箱，其中ain,bin,cin信号可采用实验箱上SW0,SW1,SW2键作为输入，并将输入的信号连接到红色LED管LEDR0,LEDR1,LEDR2上便于观察，sum,cout信号采用绿色发光二极管LEDG0,LEDG1来显示。图1.1 全加器原理图
it s a protel (2011-12-17, VHDL, 2KB, 下载3次)

http://www.pudn.com/Download/item/id/1734424.html

[VHDL/FPGA/Verilog] FADDER

vhdl一位全加器由两个半加器和一个或门组成
This is a vhdl of udcnt4 (2011-12-06, VHDL, 272KB, 下载4次)

http://www.pudn.com/Download/item/id/1722817.html

[VHDL/FPGA/Verilog] 16bitALU

一个16位ALU设计，该ALU主要能实现算术运算(加、减、带进位加、带进位减、加1、减1、传输)、逻辑运算(与、或、非、异或、同或、逻辑左移、逻辑右移操作)。
16bitALU vrilog Code (2011-01-04, VHDL, 1KB, 下载11次)

http://www.pudn.com/Download/item/id/1402071.html

[VHDL/FPGA/Verilog] ledxianshizidongjia

数码管动态显示4位数字自动加实现数码管的显示，4位自动加
LED dynamic display 4-digit automatic (2010-11-28, C/C++, 13KB, 下载4次)

http://www.pudn.com/Download/item/id/1361377.html

[VHDL/FPGA/Verilog] 07401200310

VHDL原程序包括译码器，半加器，全加器
VHDL program, including the original decoder, the half adder, full adder (2010-10-23, VHDL, 342KB, 下载11次)

http://www.pudn.com/Download/item/id/1325264.html

[VHDL/FPGA/Verilog] tbooth_pipeline

布斯算法 2000 布斯算法 2000 布斯算法 2000 布斯算法 2000 布斯算法 2000
Booth 2000 Booth algorithm algorithm algorithm 2000 Booth 2000 Booth 2000 Booth algorithm algorithm 2000 (2010-05-11, VHDL, 1KB, 下载3次)

http://www.pudn.com/Download/item/id/1167185.html

[VHDL/FPGA/Verilog] Manchester

曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档
Manchester Encoder-Decoder (2009-10-15, VHDL, 40KB, 下载171次)

http://www.pudn.com/Download/item/id/938779.html

[VHDL/FPGA/Verilog] adder

一位全加器可由两个一位半加器与一个或门构成，该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路
A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical description method, first of all the design half-adder circuit, be packaged as a half-adder module and then call at the top half-adder composed of full-adder circuit modules (2009-10-08, VHDL, 154KB, 下载22次)

http://www.pudn.com/Download/item/id/932023.html

[VHDL/FPGA/Verilog] hadder

这是一个8位全加器，利用vhdl完成了电路的构成，
this is a 8 bit adder, (2009-04-27, VHDL, 155KB, 下载2次)

http://www.pudn.com/Download/item/id/734041.html

[VHDL/FPGA/Verilog] adder1

一个全加器的VHDL程序,经过编译和仿真.
A full adder of the VHDL program, after compiling and simulation. (2008-11-11, VHDL, 149KB, 下载62次)

http://www.pudn.com/Download/item/id/577615.html

[VHDL/FPGA/Verilog] fulladder

全加器,有半加器和或门组成.元件例化语句.
Full adder, half adder and OR gate components. Components of sentence cases. (2008-01-09, Others, 12KB, 下载4次)

http://www.pudn.com/Download/item/id/390970.html