维加斯16687406569客服下载搜索联合开发网

[VHDL/FPGA/Verilog] fpga_hiwi

fpga高维
fpga hiwi (2023-12-01, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1701696634738580.html

[VHDL/FPGA/Verilog] MTRX3700_ASSIGNMENT_1

维罗格，
VERILOG, (2023-09-07, SystemVerilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1694086256952011.html

[VHDL/FPGA/Verilog] sphinx-vhdl

斯芬克斯vhdl，，
sphinx-vhdl,, (2022-11-07, Python, 24KB, 下载0次)

http://www.pudn.com/Download/item/id/1667784102744955.html

[VHDL/FPGA/Verilog] aes-cPP-and-verilog

AES算法加解密系统,毕业设计源代码,包括Verilog源代码文件
AES algorithm encryption and decryption system (2017-04-26, C++, 787KB, 下载11次)

http://www.pudn.com/Download/item/id/1493208296734477.html

[VHDL/FPGA/Verilog] lvboqiquzaosheng

滤波器去除噪声以及加随机噪声，显示图形fir滤波器
Filter to remove the noise and random noise, graphic display (2015-05-05, Flex, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1430812302724934.html

[VHDL/FPGA/Verilog] adder5

5位全加器，与4位全加器相比较对新手来说更能深刻的理解Verilog语言。
5 bit full adder, compared with a 4 bit full adder for the novice can be more profound understanding of Verilog language. (2014-06-27, VHDL, 2744KB, 下载4次)

http://www.pudn.com/Download/item/id/2576350.html

[VHDL/FPGA/Verilog] add

一位全加器　　　一位全加器(FA)的逻辑表达式为：　　　S＝A⊕B⊕Cin；　　　Co＝AB＋BCin＋ACin。其中A,B为要相加的数，Cin为进位输入；S为和，Co是进位输出；如果要实现多位加法可以进行级联，就是串起来使用；比如32位+32位，就需要32个全加器。
A full adder is a logical expression of the full adder (FA): S = A ⊕ B ⊕ Cin Co = AB+ BCin+ ACin. Wherein A, B for the number to be added, Cin for the carry bit input S is and, Co is the carry output if you want to achieve many of the adder can be cascaded is string together use instance 32+32 bit, you need 32 a full adder. (2013-01-24, VHDL, 97KB, 下载10次)

http://www.pudn.com/Download/item/id/2126437.html

[VHDL/FPGA/Verilog] umattlab_fills

运用自适应LMS 算法，，实现FIR最佳维纳滤波器。
Use of the adaptive LMS algorithm to achieve optimal FIR Wiener filter. (2012-07-26, Visual C++, 4KB, 下载8次)

http://www.pudn.com/Download/item/id/1949393.html

[VHDL/FPGA/Verilog] banjiaqisheji

半加器设计。有用的实验操作报告。EDA有详细的操作步骤
Half adder design. Useful experimental operation report. Detailed steps in EDA (2012-05-23, VHDL, 635KB, 下载6次)

http://www.pudn.com/Download/item/id/1883638.html

[VHDL/FPGA/Verilog] add_4

4位串联全加器的fpga实现，由4个一位全加器组成
Four series of fpga realizing the QuanJia by 4 a QuanJia emulators (2012-05-06, VHDL, 12KB, 下载3次)

http://www.pudn.com/Download/item/id/1857780.html

[VHDL/FPGA/Verilog] ls139

全加器程序编写，用VHDL语言实现四位全加器的加法运算
Full adder programming, using VHDL language to achieve the addition of four full-adder operation (2011-12-13, VHDL, 24KB, 下载2次)

http://www.pudn.com/Download/item/id/1729482.html

[VHDL/FPGA/Verilog] shuzizhong

数字钟，数码管显示星期时间，4键为复位，1键加2键为加时间，1加3为减时间
Digital clock, digital display weeks, 4 button to reset a key plus 2 keys for added time, plus 3 to minus 1 time (2011-06-09, Visual C++, 53KB, 下载4次)

http://www.pudn.com/Download/item/id/1564112.html

[VHDL/FPGA/Verilog] half_adde

半加器源代码，用VHDL语言编写有需要的可以看看
Half adder source code, using VHDL language need to look at (2010-05-12, VHDL, 119KB, 下载4次)

http://www.pudn.com/Download/item/id/1168420.html

[VHDL/FPGA/Verilog] CPLD

用vga显示俄罗斯方块基于fpga但是不是真正的游戏俄罗斯方块
Tetris with vga display based on the fpga, but not a true game Tetris (2010-02-02, VHDL, 2250KB, 下载64次)

http://www.pudn.com/Download/item/id/1057026.html

[VHDL/FPGA/Verilog] f__adder

全加器，半加器，或语句，三个建在一个文件中就可以用了
Full adder, half adder, or statement, three built in one file can be used (2009-03-27, VHDL, 1KB, 下载25次)

http://www.pudn.com/Download/item/id/691013.html

[VHDL/FPGA/Verilog] 1

1位全加器的vhdl设计通过两个半加起实现
A full adder of VHDL design increases since the adoption of two and a half to achieve (2008-12-15, VHDL, 109KB, 下载4次)

http://www.pudn.com/Download/item/id/605916.html

[VHDL/FPGA/Verilog] fadder4

VHDL实现四位全加器，适合初学者，源程序下载
VHDL realization of four full adder, suitable for beginners, the source code download (2008-04-29, VHDL, 110KB, 下载17次)

http://www.pudn.com/Download/item/id/448955.html

[VHDL/FPGA/Verilog] Manchester

基于FPGA/CPLD，采用VHDL语言的曼彻斯特的编解码实现。还包含曼彻斯特码的说明文档。
Based on FPGA/CPLD, using VHDL language codec Manchester realize. Manchester code also includes documentation. (2008-03-08, Others, 171KB, 下载272次)

http://www.pudn.com/Download/item/id/412670.html

[VHDL/FPGA/Verilog] myproject

四位全加器，VHDL语言，max+plusII平台做的
Four full-adder, VHDL language, max+ PlusII platform to do (2007-12-02, Others, 55KB, 下载11次)

http://www.pudn.com/Download/item/id/368554.html

[VHDL/FPGA/Verilog] manchesterdecoder

曼彻斯特解码程序，用VHDL语言编写，和编码程序配套使用
Manchester decoding procedures, using VHDL language, and coding procedures for supporting the use of (2007-10-10, Others, 1KB, 下载53次)

http://www.pudn.com/Download/item/id/343346.html