伊维里洛api
iverilog api (2024-01-24, Others, 0KB, 下载0次)
半加器和全加器的Quartus II文本输入设计及其仿真波形
Text input design and simulation waveform of Quartus II for half adder and full adder (2020-05-22, Quartus II, 5KB, 下载0次)
基于FPGA的AES算法数据加解密设计_陈彦龙
The AES algorithm based on FPGA design _ drogen data encryption (2016-03-29, Visual C++, 6239KB, 下载4次)
用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。
Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full adder. (2014-09-16, VHDL, 98KB, 下载3次)
这个工程是实现HDB3码的编码功能,可分别输入加V、加B以及最终的HDB3码
This project is to achieve HDB3 code encoding function (2013-12-17, VHDL, 5720KB, 下载8次)
在赛灵思软件ISE上实现的ＡＥＳ加解密算法，并且在ＭＯＤＥＬＳＩＭ上仿真。希望对你有所帮助
The Xilinx software ISE AES encryption and decryption algorithms, and simulation MODELSIM on. I hope for your help (2013-04-15, VHDL, 79KB, 下载8次)
巴特沃斯滤波器的Verilog实现，基于matlab
Butterworth filter Verilog implementation based on matlab (2012-12-01, VHDL, 6KB, 下载16次)
通过调用半加器模块，实现全加器设计，含测试代码，通过验证
By calling the module of the half adder full adder design, with test code, by verifying (2012-06-25, VHDL, 189KB, 下载3次)
一位半加器工程，用xilinx ISE设计，供初学者学习
A half adder project using xilinx the ISE design for beginners to learn (2012-06-24, VHDL, 117KB, 下载2次)
曼彻斯特编码的verilog实现,复制到quartus II可用
Manchester verilog realize the code,Copy to quartus II available
(2011-11-24, Others, 10KB, 下载84次)
曼彻斯特和差分曼彻斯特编码的实现 分析：曼彻斯特编码是将每个码元的中央实现跳变，具体的码字表示为：1->10,0->01.
Direct code (2011-10-08, Visual C++, 2KB, 下载39次)
四位元全加器,為Verilog/VHDL構成的IP模組電路
4bit fulladder (2011-09-15, VHDL, 12KB, 下载5次)
曼切斯特编码器的有一种verilog实现，附带有仿真波形，和时序分析
verilog (2010-12-20, VHDL, 10KB, 下载24次)
由四位全加器通过元件例化语句设计成十六位的全加器
By four full adder component instantiated by statements designed 16 of the full adder (2010-07-27, VHDL, 518KB, 下载12次)
基于VHDL的曼彻斯特编解码的设计程序及仿真波形
Manchester code (2010-05-30, VHDL, 304KB, 下载47次)
加德罗域乘法器提供了一种新型的乘法器设计模式
Multiplier加德罗domain to provide a new design of the multiplier model (2009-07-09, VHDL, 2KB, 下载9次)
1位全加器 可以进行1位的二进制码的加法 想进行改进 改为4位或8位的全加器代码
A full adder can be an addition of the binary code would be changed to improve the 4 or 8-bit full adder code (2009-04-15, VHDL, 2KB, 下载42次)
用例化语句和case语句编写的全加器的VHDL描述。
Of statements were prepared using the full adder of the VHDL description. (2009-04-12, VHDL, 63KB, 下载4次)
曼彻斯特编码实现，verilog HDL 做的，我也是从网上下的
Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under (2008-11-30, VHDL, 1KB, 下载169次)
曼彻斯特编解码，是Verilog语言代码，不多介绍了，用途非常广泛了
Manchester encoding and decoding is the Verilog language code, introduced a few, a very extensive use (2006-10-11, Others, 9KB, 下载79次)