ARC4加解密实验室
ARC4 Encryption Decryption Lab (2018-05-22, SystemVerilog, 51198KB, 下载0次)
P4 NetFPGA维基
P4-NetFPGA wiki (2018-02-26, Others, 70405KB, 下载0次)
数电实验FPGA verilog代码，包括秒表、全加器、半加器等。
FPGA Verilog code for digital experiment (2020-04-29, Verilog, 8KB, 下载1次)
123eweqs撒撒打算阿斯达十大是的阿迪斯
123fsdfsadssssssssssss (2017-08-22, Java, 600KB, 下载1次)
布斯乘法器设计源码。。功能完善，modelsim仿真通过
Booth Multiplier source. . Perfect function, modelsim simulation through (2016-06-23, VHDL, 3KB, 下载6次)
8位全加器，为EDA的第一个实验，由半加器和或门组成
8 full adder bit EDA experiment first simple experiment, through the OR gate constructed with half-adder (2015-02-07, VHDL, 255KB, 下载1次)
4位全加器由3个模块构成。首先，通过实例引用基本门级元件xor、and定义底层的半加器模块halfadder，接着实例引用两个半加器模块halfadder和一个基本或门元件or组合成为全加器模块fulladder，最后实例引用4个1位的全加器模块fulladder构成4位全加器的顶层模块
4 full adder by the three modules. First, the basic gate-level component instance references xor, and define the underlying half-adder module halfadder, then cite two examples of half-adder module halfadder and a base or gate element or combination of a full adder module fulladder, the last instance references 4 a one of the full adder module fulladder constitute four full adder top module (2013-08-18, VHDL, 393KB, 下载2次)
利用matlab，对偏振控制器进行仿真，最终在邦加球上进行显示
Using matlab, simulation of the polarization controller eventually be displayed on the Poincare Sphere (2013-04-07, matlab, 1KB, 下载57次)
介绍了verilog HDL语言对AES算法进行数据加解密。
Introduced the verilog HDL language to AES algorithm for data encryption and decryption. (2012-11-05, VHDL, 76KB, 下载81次)
ISE工程 包含各种基本部件 全加器 寄存器 解码器等等
The ISE project includes various basic components of the full adder register decoder (2012-09-01, VHDL, 2458KB, 下载5次)
实现一位全加器的运算，并通过调用模块实现四位全加器的运算
Implement a full adder operation, and by calling the module' s operation four full adder (2011-07-21, Others, 174KB, 下载10次)
EDA实验中的全加器的VHDL语言的实现，包含半加器、全加器、JK触发器、D触发器以及50m分频的源程序
EDA test full adder in VHDL language implementation, including the half adder, full adder, JK flip-flop, D flip-flop and the frequency of the source 50m (2011-05-03, VHDL, 1286KB, 下载7次)
整数模加器的一种硬件设计方法,在深入分析模加运算的实现基础上，提出了一种模加运算的实现方案，并论证了该方案的正确性。基于这种实现方案．设计并验证了一块实现l6位模加运算的逻辑电路，仿真结果表明了电路的正确性和设计方案的可行性。
A hardware design method of integer modular adder. (2010-01-14, VHDL, 709KB, 下载7次)
用VHDL语言设计四位全加器，有低位进位和高位进位。
VHDL language with four full-adder design, there are low and the high binary binary. (2009-04-16, VHDL, 2KB, 下载26次)
8位全加器的VHDL语言描述，有需要的顶一下。
8-bit full adder described in the VHDL language, there is a need to click the top. (2009-04-04, VHDL, 115KB, 下载7次)
曼彻斯特编码的VHDL源程序?顾固乇嗦氲腣HDL源程序
Manchester-coded VHDL source code? Gu SOLID乇winded heavy atmosphere腣HDL source (2008-07-12, VHDL, 10KB, 下载39次)
verilog加法器,附加测试文件
可用modelsim 仿真实现
Verilog Adder, additional test file ModelSim simulation can be used to achieve (2007-12-01, Others, 5KB, 下载359次)
4位全加器原码，包括仿真码和4位计数器码。
four full adder original code, including the simulation code and four counter code. (2007-04-14, WORD, 3KB, 下载12次)
实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。
experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting. (2006-08-13, Others, 59KB, 下载75次)
用cpld实现曼彻斯特编码
用verilog HDL进行曼彻斯特编码，用于通信中
cpld achieve with Manchester encoding with Verilog HDL Manchester encoding. for Communication (2006-01-14, Windows_Unix, 4KB, 下载194次)