冲突以太网MAC tinytapeout模块
Clash ethernet MAC tinytapeout module (2024-05-04, Verilog, 0KB, 下载0次)
USB以太网FPGA卡
USB-Ethernet FPGA card (2023-11-11, Verilog, 0KB, 下载0次)
多流以太网带宽控制，
Multi-Stream Ethernet Bandwidth Control, (2020-01-14, Verilog, 0KB, 下载0次)
人工网表生成器，
Artificial Netlist Generator, (2023-03-13, Verilog, 0KB, 下载0次)
牛客网刷题记录,
Niuke.com question brushing record, (2023-08-19, Verilog, 0KB, 下载0次)
符合IEEE 802.3的以太网MAC
An Ethernet MAC conforming to IEEE 802.3 (2017-05-13, Verilog, 6412KB, 下载0次)
亿龙网FPGA-10G回购
Yilong s NetFPGA-10G Repo (2015-05-07, Verilog, 59954KB, 下载0次)
FPGA 百兆以太网
FPGA 100 Gigabit Ethernet (2019-02-23, Verilog, 33932KB, 下载0次)
NESTang是一款用Sipeed Tang Nano 20K和Primer 20K板实现的FPGA任天堂娱乐系统
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Nano 20K and Primer 20K boards (2023-05-19, Verilog, 758KB, 下载0次)
Verilog以太网交换机（第2层）
Verilog Ethernet Switch (layer 2) (2021-07-27, Verilog, 147KB, 下载0次)
以太网MAC 10 100 Mbps
Ethernet MAC 10 100 Mbps (2019-10-02, Verilog, 978KB, 下载0次)
用于FPGA实现的Verilog以太网组件
Verilog Ethernet components for FPGA implementation (2023-05-02, Verilog, 2375KB, 下载0次)
基于spatan6 x16 平台的以太网收报程序 (2022-04-26, Verilog, 104KB, 下载0次)
http://www.pudn.com/Download/item/id/1650987480972703.html
三态以太网MAC控制器，支持10M/100M/1000M三种速率，采用wishbone总线
Three state Ethernet MAC controller, supporting 10m / 100M / 1000m three rates, using wishbone bus (2020-12-12, Verilog, 1135KB, 下载1次)
千兆以太网，GMII口，udp模式传输数据，fpga控制
Gigabit Ethernet, gmii port, UDP mode data transmission, FPGA control (2020-09-11, Verilog, 9KB, 下载5次)
使用Verilog编写的管理以太网PHY的MDIO接口的控制器，在小梅哥AC620、AC6102开发板上验证通过，可以成功设置PHY芯片的链接速度到指定的速率。
The controller for managing the MDIO interface of Ethernet PHY written by Verilog has been verified on the development boards ac620 and ac6102 of xiaomeige, and can successfully set the link speed of phy chip to the specified speed. (2020-03-12, Verilog, 3KB, 下载21次)
对新手学习SRIO接口通信，有一定的帮助。希望能够获得更多这方面的进展。
It is helpful for novices to learn SRIO communication (2018-12-05, Verilog, 1469KB, 下载13次)
用FPGA，基于M88E1111芯片实现的TCP/IP协议的千兆网，将协议封装成IP核
With the FPGA, the TCP/IP protocol based on the M88E1111 chip is used to encapsulate the protocol into IP core (2018-02-08, Verilog, 18855KB, 下载53次)
千兆网学习代码 ISE，状态机实现数据打包，基于PHY芯片实现数据传输
ethernet communication sample with verilog,state machine (2018-01-03, Verilog, 6940KB, 下载2次)
用FPGA 编写的双端口的RAM，可以实现读写，希望通过这个平台与各个大神交流，希望得到大神的批评指正。
Prepared by FPGA double port RAM, you can read and write, and I hope that through this platform to communicate with the great gods, hoping to get criticism of the great god. (2017-08-10, Verilog, 7227KB, 下载4次)