FPGA以太网入门(三)——UDP测试实验(基于紫光同创)
Introduction to FPGA Ethernet (III) - UDP test experiment (based on Purple Light Co creation) (2024-03-04, Verilog, 0KB, 下载0次)
基于FPGA的三速以太网UDP协议栈设计
Design of Three Speed Ethernet UDP Protocol Stack Based on FPGA (2024-01-18, Verilog, 0KB, 下载0次)
在没有处理器的情况下使用以太网FMC的示例设计（即基于状态机），
Example designs for using Ethernet FMC without a processor (ie. state machine based), (2023-10-26, Verilog, 0KB, 下载0次)
针对Terasic DE2-115和Marvell 88E1111 PHY的以太网中继器的SystemVerilog实现，
A SystemVerilog implementation of a Ethernet Repeater targeting a Terasic DE2-115 and Marvell 88E1111 PHY, (2023-04-29, Verilog, 0KB, 下载0次)
TrojanSAINT：用于硬件木马检测的基于门级网表采样的归纳学习，
TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection, (2023-08-23, Verilog, 0KB, 下载0次)
纳斯达克HFT FPGA项目低延迟以太网模块的RTL实现。，
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project., (2023-08-12, Verilog, 0KB, 下载0次)
OpenCores三模以太网MAC的AXI4 LITE缓冲区。包括SIM卡。
AXI4 LITE buffer for the OpenCores Trimode Ethernet MAC. Includes SIM. (2015-12-22, Verilog, 17191KB, 下载0次)
用于以太网“软”MAC实验的集成802.3u PHY的FPGA板
FPGA board with integrated 802.3u PHY for Ethernet "soft" MAC experimentation (2022-12-20, Verilog, 220KB, 下载0次)
在Cyclone IV FPGA上使用1000BASE-T以太网的未压缩视频uver UDP
Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA (2021-02-22, Verilog, 67KB, 下载0次)
基于FPGA的可编程多10千兆以太网网络测试仪
Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet (2020-02-04, Verilog, 293KB, 下载0次)
通过以太网将数据从ADC传输到PC
Transfers data from an ADC to a PC via ethernet (2018-06-07, Verilog, 6029KB, 下载0次)
使用GHDL将NEORV32处理器转换为可合成的纯Verilog网表模块。
Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. (2023-05-15, Verilog, 11KB, 下载0次)
一个16点基-4 FFT芯片，包括Verilog代码、网表和布局。集团项目。
A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project. (2020-05-16, Verilog, 44475KB, 下载0次)
带DMAC和以太网控制器的picorv32 riscv Soc&lwip&Kirtex7@333MHz
A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz (2021-06-10, Verilog, 2954KB, 下载0次)
实现V5系列的FPGA与上位机的千兆以太网口通信
Realize the communication between FPGA of V5 series and host computer through Gigabit Ethernet port (2021-03-25, Verilog, 3KB, 下载0次)
通过RGMII协议驱动的PHY芯片完成千兆以太网收发，包括ARP响应
With RGMII driving PHY IC to finish the internet communication (2020-08-05, Verilog, 4253KB, 下载7次)
通过网口UDP协议，接收上位机控制命令，用于控制转台状态，并通过串口读取并通过网口上传转台工作状态
Through the network port UDP protocol, receive the upper computer control command, used to control the status of the turntable, and read through the serial port and upload the working state of the turntable through the network port (2020-07-18, Verilog, 15877KB, 下载3次)
网口UDP的FPGA仿真代码，经过测试能够实现预想功能
etherneit udp verilog fpga code (2020-05-26, Verilog, 128KB, 下载7次)
SPI接口代码实现，有需要的可以自行下载
SPI interface code implementation (2018-05-24, Verilog, 1KB, 下载2次)
基于Wiznet公司的W5300以太网解决方案，完成以太网通讯设计。该项目代码基于浩然电子的HS-NM5300A模块调试，可直接使用。
Based on Wiznet's W5300 Ethernet solution, complete the Ethernet communication design. The project code based on Hao Ran electronic HS-NM5300A module debugging, can be used directly. (2017-10-13, Verilog, 2272KB, 下载62次)