The source code of Verilog HDL数字系统设计与验证 ——以太网交换机案例分析
The source code of Verilog HDL digital system design and verification -- Ethernet switch case study (2023-12-06, Verilog, 0KB, 下载1次)
一种测试设计，旨在了解如何在小型FPGA设计中使用三模式以太网MAC。，
A test design to see how the Tri-mode Ethernet MAC can be used in a small FPGA design., (2023-09-07, Verilog, 0KB, 下载0次)
创建了Qsys系统，包括Nios II、三速以太网IP核、SGDMA控制器和其他用于传输的硬件组件...，
Created Qsys system that includes Nios II, Triple-Speed Ethernet IP Core, SGDMA controller and other hardware components for transmit and receive operation. Two Phase-Locked Loop modules are added to the design to generate clocks with different frequencies to make the Triple-Speed Ethernet system (which implements the MAC function) work (2017-01-03, Verilog, 0KB, 下载0次)
加法器-计数器-乘法器-除法器-CRC移位器verilog模型，具有RTL和门级网表，
adder counter multiplier divider CRC shifter verilog model, with RTL and gate level netlist, (2023-05-15, Verilog, 0KB, 下载0次)
一种用于3D IC设计的基于GPT-GNN的verilog网表划分器，
A GPT-GNN based verilog netlist partitioner for 3D IC design, (2022-11-14, Verilog, 0KB, 下载0次)
使用FPGA同时捕获来自多个ADC的数据。通过以太网+UDP流式传输捕获的数据。已测试...
Capture data from multiple ADCs concurrently using an FPGA. Stream the captured data out over ethernet + UDP. Tested on the Spartan 6 XC6SLX9, Wiznet W5500, and MCP3002 ADC. (2016-12-10, Verilog, 14KB, 下载1次)
ECE 385最终项目——基于MAX10 DE10 Lite FPGA和Nios II软处理器的以太网
ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor (2021-12-13, Verilog, 8778KB, 下载0次)
生成给定Verilog Quartus Mapping（VQM）网表中所有节点的逗号分隔值（CSV）文件及其...
generates a Comma-Separated Values (CSV) file of all nodes in a given Verilog Quartus Mapping (VQM) netlist and their respective fanouts, ordered by fanout (highest first) (2017-04-25, Verilog, 498KB, 下载0次)
“基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片，并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限，只能存储分辨率较小的图片
In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution (2021-03-21, Verilog, 9441KB, 下载1次)
在图像处理领域，光线是非常重要的前提。灯源最好是环形灯，就像那些网红给自己打光一样，环形灯光照均匀。
WS2812B-LED环形灯工作时序
In the field of image processing, light is a very important premise. The best light source is the ring lamp, just like those net red lights, the ring light is uniform.
Working sequence of ws2812b-led ring lamp (2021-01-23, Verilog, 345KB, 下载0次)
数电实验FPGA verilog代码，包括秒表、全加器、半加器等。
FPGA Verilog code for digital experiment (2020-04-29, Verilog, 8KB, 下载1次)
5G DU与RU间采用 eCPRI协议，ecpri 规范的范围是通过基于数据包的前端传输网络 (如 ip 或以太网) 实现高效、灵活的无线电数据传输。ecpri 定义了一个协议层, 它为协议堆栈的上层提供各种--主要是用户平面数据的特定--服务。
eCPRI protocol used in 5G Du and Ru (2020-04-01, Verilog, 1506KB, 下载10次)
基于EDA实验箱实现空气净化器五大功能：
自动模式 手动模式 睡眠模式 定时模式及提醒更换滤网功能。
本程序计时部分存在问题 其他功能均可实现
Based on EDA experimental box, five functions of air purifier are realized: automatic mode, manual mode, sleep mode, timing mode and reminding function of changing filter screen.
Problems in the timing part of this program and other functions can be realized (2019-07-04, Verilog, 793KB, 下载0次)
多种基本功能的Verilog代码实现，包括多路选择器，二进制到BCD码转换，二进制到格雷码转换，7段译码器，8位数据锁存器，移位寄存器等等多种功能。
Verilog code implementation of a variety of basic functions, including multiplexer, binary to BCD code conversion, binary to Gray code conversion, 7-segment decoder, 8-bit data latch, shift register and many other functions. (2019-06-08, Verilog, 18KB, 下载3次)
经典的verilog语言实现ICMP协议的参考代码
Reference Code of ICMP Protocol Implemented by Classical Verilog Language (2019-03-19, Verilog, 979KB, 下载5次)
详细的网口协议芯片器件资料，是开发该器件的必备资料
Detailed device information is essential for the development of the device. (2018-12-27, Verilog, 694KB, 下载15次)
实现SPI总线接口转I2S总线接口数据传输
achieve spi bus to I2s bus by verilog (2018-09-14, Verilog, 90KB, 下载4次)
A/D采集的数据缓存进入fifo，并通过读信号将FIFO中的数据送入网口
A/D sample data buffer to fifo,and then read enable to ethernet. (2017-10-23, Verilog, 1KB, 下载21次)
功能验证了 8211EG千兆网卡 联合XilinxFPGA 的网卡数据发送数据 可广播 可单播
The function verifies that the network card data of 8211EG gigabit and XilinxFPGA can be broadcast on a single broadcast (2017-10-23, Verilog, 6086KB, 下载2次)
Altera公司出的三速以太网例程，工程编译完了可以用niosii直接生成simple_socket_server，希望有用。
Altera company out of the three speed Ethernet routines, engineering finished, you can directly generate simple_socket_server using NiosII, I hope useful. (2017-09-16, Verilog, 1133KB, 下载20次)