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按平台查找All Verilog(124) 

[VHDL/FPGA/Verilog] 开源软核处理器OPENRISC的SOPC设计

《开源软核处理器OpenRisc的SOPC设计》介绍基于源代码开放的OpenRisc1200(以下简称OR1200)软核处理器的SOPC设计方法。《开源软核处理器OpenRisc的SOPC设计》分为两部分,第一部分介绍OR1200软核处理器的架构和配置、Wishbone总线的标准及OR1200软核处理器软硬件开发环境的建立;第二部分以具体实例说明如何使用OR1200软核处理器完成嵌入式设计,其中包括:调试接口的实现、OR1200控制片内存储器和I/O、串口、SDRAM、外部总线、以太网、LCD及SRAM;另外还介绍如何在OR1200上运行嵌入式Linux,并针对第二部分给出部分源代码。 《开源软核处理器OpenRisc的SOPC设计》适合对SOPC或OR1200软核处理器感兴趣的初学者使用,也可作为嵌入式系统设计人员的自学用书,或作为相关专业研究生的教材和教师的教学参考书。
Open source processor design method based on openriscor1200. The SOPC design of open source soft core processor openrisc is divided into two parts. The first part introduces the architecture and configuration of or1200 soft core processor, wishbone bus standard and the establishment of software and hardware development environment of or1200 soft core processor. The second part describes how to use or1200 soft core processor to complete embedded design with specific examples, including the implementation of debugging interface and or1200 control In addition, it introduces how to run embedded Linux on or1200, and gives some source codes for the second part. SOPC design of open source soft core processor openrisc is suitable for beginners who are interested in SOPC or or1200 soft core processor. It can also be used as a self-study book for embedded system designers, or as a teaching reference book for graduate students and teachers. (2020-10-27, Verilog, 11722KB, 下载3次)

http://www.pudn.com/Download/item/id/1603781530127775.html

[VHDL/FPGA/Verilog] FPGA_AutoControl_Xiyiji_by_Jalen_Cheng

可编程数字系统设计的基本流程 设计输入(原理图文件、硬件描述语言文件、网表输入文件、混合输入文件)项目处理(设计文件检查和编译、设计文件分析和综合、器件适配、设置设计约束)设计校验(生成功能网表、功能仿真、适配后的仿真文件、门级时序仿真)器件编程(生成器件编程文件、器件编程) 原理设计输入方式是利用软件提供的各种原理图库,采用画图的方式进行设计输入。这是一种最为简单和直观的输入方式。原理图输入方式的效率比较低,一般只用于小规模系统设计,或用于在顶层拼接各个已设计完成的电路子模块。
Basic Flow of Programmable Digital System Design Design Input (schematic diagram file, hardware description language file, netlist input file, mixed input file) project processing (checking and compiling design documents, analysis and synthesis of design documents, device adaptation, setting design constraints) design verification (generating functional netlist, function simulation, adapted simulation files, gate-level timing simulation) device programming (generating component programming text) Programming of Components and Devices Principle design input mode is to use various schematic library provided by the software to design input by drawing. This is the simplest and most intuitive way to input. The input mode of schematic diagram is inefficient. It is usually only used for small-scale system design or for splicing each completed circuit sub-module at the top level. (2018-12-24, Verilog, 6632KB, 下载1次)

http://www.pudn.com/Download/item/id/1545656216831029.html

[其他] mux四选一

mux四选一及译码器:MUX电路在数字集成电路被广泛使用,作为寄存器或者其他电路的输入选择控制。也是ASIC设计中的基本门电路之一。
MUX four selection one and decoder (2017-12-06, Verilog, 2KB, 下载2次)

http://www.pudn.com/Download/item/id/1512528603824357.html

[VHDL/FPGA/Verilog] 27个FPGA实例源代码

一些对初学者比较实用的源码,ASK,PSK,FSK调制解调
Some of the more practical source code for beginners (2017-10-15, Verilog, 1251KB, 下载52次)

http://www.pudn.com/Download/item/id/1508070310692921.html
总计:124