用于软核FPGA RISC-V项目的简单RISC-V.汇编程序。，
Simple RISC-V assembler for a soft-core FPGA RISC-V project., (2023-10-24, C++, 0KB, 下载0次)
一个交互式VGA显示程序使用ZedBoard的可编程FPGA和桌面上的C++来控制VGA显示...
An interactive VGA display program using a ZedBoard s programmable FPGA and C++ on the desktop to control a VGA display, by Thomas Douglas and Aaditya Watwe. (2020-01-13, C++, 11293KB, 下载0次)
用于固定可编程门阵列（FPGA）的高级合成的源代码。可以使用Vivado转换为RTL...
Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC. (2019-04-05, C++, 27KB, 下载0次)
基于Zynq-7000 FPGA结构的可编程逻辑（HW）优化Canny边缘检测器算法
Canny Edge detector algorith optimized on the Programmable Logic (HW) of the Zynq-7000 FPGA Architecture (2020-06-03, C++, 16178KB, 下载0次)
示例显示为教程“使用高级合成在FPGA上进行高效并行编程”的一部分。
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis". (2021-11-14, C++, 44KB, 下载0次)
Verilog中的逻辑设计，现代计算机体系结构中涉及的MIPS汇编程序和优化方法。
Logic design in Verilog, MIPS assembly programs and optimization methods involved in modern computer architecture. (2021-02-01, C++, 5459KB, 下载0次)
FPGA汇编程序！在没有Verilog或VHDL的情况下创建裸金属FPGA设计（不要自行：下次使用Lisp）
FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time) (2021-07-22, C++, 67KB, 下载0次)
bnn-fpga是FPGA上CIFAR-10的二进制神经网络（BNN）加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC，并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时，错误率是11.19％。
bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%. (2020-07-27, C++, 318KB, 下载5次)
每个I/O端口位可以自由编程，然而I/0端口寄存器必须按32位字被访问(不允许半字或字节访问)。
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed
as 32-bit words (half-word or byte accesses are not allowed). (2013-11-29, C++, 540KB, 下载2次)
设计背景:近年来现场可编程门阵列( FPGA) 技术得到了迅速的发展和广泛的应用, 其资源容量、工作频率以及集成度都得到了极大的提高, 使得利用FPGA 实现某些专用数字集成电路得到了大家的关注, 而基于FPGA 实现的直接数字频率合成器即DDS（Direct Digital Synthesizer）则更具其优点, 有着灵活的接口和控制方式、较短的转换时间、较宽的带宽、以及相位连续变化和频率分辨率较高等优点, 其也为设计者在此基础之上实现电路集成提供了另一种方法,同D/ A 转换器和低通滤波器( LPF) 一起便可以组成任意波形信号的发生器。
Design background: in recent years field programmable gates array (FPGA) technology obtained A rapid development and extensive application of its resource capacity, working frequency and integration have been greatly improved, make use of FPGA realizing some special Digital integrated circuit got everyone s attention, and based on FPGA realizing Direct Digital frequency Synthesizer namely Direct Digital Synthesizer (DDS) is more the advantages, has the flexible interface and the control mode, A relatively short period of time, A wide conversion bandwidth, and phase change and continuous frequency resolution higher advantages, its also to designers based on integrated circuit to realize provides an alternative method, with the D/A converter and low pass filter (together) and can form LPF of arbitrary wave form of signal generator. (2011-08-13, C++, 74KB, 下载18次)