题目2：设计一个表决器
要求： 实现参数化表决功能， 可配置为 3、 5、 7， 2K+1 人（人数<16）表决功能，多数人表决通过则通过；
题目2：设计一个表决器
要求： 实现参数化表决功能， 可配置为 3、 5、 7， 2K+1 人（人数<16）表决功能，多数人表决通过则通过； (2022-05-05, Quartus II, 304KB, 下载0次)
121奥术大师大所多撒大所多a's萨达所大
who is your daddy and why (2020-10-22, Quartus II, 221KB, 下载0次)
在Quartus 上实现一个二选一数据选择器，希望有帮助
It is hoped that the implementation of a data selector on quartus will help. (2020-06-17, Quartus II, 2744KB, 下载1次)
一个十六进制的计数器，以CLK为输入信号进行计数
A hexadecimal counter that counts on the input signal CLK (2020-05-16, Quartus II, 319KB, 下载0次)
加减法计数器，在设置极限数值到达时记号灯闪起，减法至0时闪烁
Addition and subtraction counter (2019-12-11, Quartus II, 3267KB, 下载0次)
Create a new Quartus Prime project with top level entity named mux2_1_struct and select the appropriate target device
Create a new Quartus Prime project with top level entity named mux2_1_struct and select the appropriate target device (2019-11-24, Quartus II, 1043KB, 下载0次)
Verolog 较为适合算法级、 寄存器传输级、逻辑级、 门级、设计。
Verilog is more suitable for algorithm level, register transfer level, logic level, gate level and design. (2019-10-28, Quartus II, 844KB, 下载0次)
分频10000倍的分频器，输入原时钟信号，输出分频10000倍后的信号
Frequency divider of 10000 (2019-05-28, Quartus II, 2KB, 下载0次)
实现时钟分频，单脉冲，计数器，并显示数码管。锁定，按键增加
Achieve the clock frequency division, monopulse, counter, and display digital tube. Lock, button increase (2018-05-22, Quartus II, 2KB, 下载1次)
FPGA上实现的的分频器，Quartus II平台，VHDL语言
The frequency divider implemented on FPGA, Quartus II platform, VHDL language. (2018-05-18, Quartus II, 102KB, 下载0次)
HC595串行移位寄存器，包括QUARTUS工程，源码和仿真测试文件
Serial shift register, including project, source code and simulation test file. (2018-05-08, Quartus II, 3157KB, 下载0次)
程序的功能是在quartus II环境下实现全加器的功能。
The function of the program is to implement the full adder function in Quartus II environment. (2018-04-26, Quartus II, 328KB, 下载1次)
程序通过采集输入信息，与FPGA的存储值进行比较，如果密码正确，则开锁电路打开；如果密码错误，锁不打开，并且计数器进行+1操作；累计3次输入密码错误，给警报一个高电平，让其报警。
By collecting input information, the program compares with the storage value of FPGA. If the password is correct, the unlocked circuit opens; if the password is wrong, the lock is not open, and the counter performs the +1 operation; the cumulative 3 time input password error gives the alarm a high level and allows the alarm to be sent to the alarm. (2018-04-26, Quartus II, 15760KB, 下载3次)
利用硬件板子上的蜂鸣器实现的新年快乐的歌曲
Using the buzzer on the hardware board to achieve a happy New Year's song. (2018-04-12, Quartus II, 580KB, 下载2次)
串行外设接口 <SPI>模块是一个同步串行接口,可用于与其他外设或者单片机进行通信。这些外设可以是串行EEPROM、移位寄存器、显示驱动器和A/D转换器等。SPI模块与Motorola的SPI和STOP接口兼容。
The serial peripheral interface <SPI> module is a synchronous serial interface, which can be used to communicate with other peripherals or MCU.These peripherals can be serial EEPROM, shift register, display drive and A/D converter, etc.SPI module is compatible with Motorola's SPI and STOP interface. (2018-03-07, Quartus II, 240KB, 下载3次)
利用EDA的Quartus2语言，实现三进八出的译码等功能。
The use of EDA Quartus2 language, to achieve three out of the eight decoding function. (2018-01-23, Quartus II, 26KB, 下载1次)
此电路是一个基于Quartus II 的加法器，由两个半加器组成。
The circuit is an adder based on Quartus II, consisting of two adder. (2018-01-11, Quartus II, 69KB, 下载1次)
特权同学开发板上的例程，DDR2控制器集成与读写测试
The routines on the privileged students' development board, DDR2 controller integration and reading and writing tests (2018-01-07, Quartus II, 538KB, 下载11次)
按一定的频率递增（0-999）
把计数值显示在数码管上
Increasing at a certain frequency (0-999)
Display the count on the digital tube (2017-12-14, Quartus II, 7919KB, 下载3次)
实现了can控制器Verilog编程使用niosII 开发平台
Can controller Verilog programming, the use of niosII development platform (2017-10-11, Quartus II, 14297KB, 下载3次)