基于fpga的多功能数字时钟 在数码管显示
verilog语言编写 可实现校时 暂停以及设定闹钟的功能
FPGA time clock (2015-05-02, VHDL, 74KB, 下载4次)
这个程序是基于Quartus II的，能通过数码管显示时、分、秒，具有闹钟的功能，能通过按键校时。
his program is based on the Quartus II, and when through digital display hours, minutes, seconds, and has an alarm clock function, button through school. (2014-11-30, VHDL, 1KB, 下载4次)
本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片，利用 VHDL 语言采用自
顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计，最后在实验箱上进行测
试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐
闹铃。
The design uses the silicon chip EP1C12Q240C8 produced by the company of
ALTERA. And with the help of VHDL, the design of a digital clock is completed
using the top-down approach under Quartus Ⅱ, finally carried out in the SmartSOPC.
Functions of the digital clock are: timer, showing day, setting time, resetting, Chime
on every hour, and alarm with music. (2014-05-20, VHDL, 226KB, 下载4次)
基于QuartusII开发环境，Cyclone III开发板的VerilogHDL多功能数字钟程序。可实现24小时计时，手动校时，闹钟，整点报时功能。分频模块在仿真和烧写是需要改变。
QuartusII based development environment, Cyclone III development board VerilogHDL multifunction digital clock procedures. Can achieve 24-hour clock, manual timing, alarm, hourly chime functions. Frequency module in the simulation and programming needs to change. (2013-07-24, VHDL, 1895KB, 下载4次)
电子时钟设计 包含校时和闹钟功能 闹钟播放一段音乐 ppt和word报告也有 太大不上传 需要的发邮箱lin170587788@gmail.com
Electronic clock and alarm functions including school play a musical alarm clock ppt and word report also does not upload much needed hair mailbox lin170587788@gmail.com (2013-06-17, VHDL, 315KB, 下载4次)
此数字钟具有时，分，秒计时并显示功能；
2.能进行24/12小时制计时模块的切换；
3.具有校时，清除功能，能对时，分，秒进行调整；
4.具有整点报时功能：在59分51秒，59分53秒，59分55秒，59分57秒发出低音256HZ信号，在59分59秒发出一次高音1024HZ信号，音响持续一秒钟，在1024HZ音响结束时刻即为整点；
This digital clock with hours, minutes, seconds, chronograph and display 2 24/12 hour time capable of switching modules 3 with the school, clean up, can the hours, minutes, seconds to adjust 4 with The whole point timekeeping functions: in 59 minutes and 51 seconds, 59 minutes and 53 seconds, 59 minutes and 55 seconds, 59 minutes and 57 seconds bass 256HZ signal sent in 59 minutes and 59 seconds to issue a treble 1024HZ signals, sound for one second, sound in 1024HZ end time is the whole point (2011-11-13, VHDL, 703KB, 下载4次)
实现超多功能数字钟的vhdl硬件实现，可以实现校时校分闹铃，多模切换，多模同时工作
Ultra-versatile digital clock vhdl hardware implementation can be achieved when the school hours the school alarm, multi-mode switching, multi-mode simultaneously (2011-08-03, VHDL, 519KB, 下载4次)
1.计时功能：包括时、分、秒的计时
2.定时与闹钟功能：能在设定的时间按发出闹铃声
3.校时功能：对小时、分钟和秒能手动调整以校准时间
4.整点报时功能
5.利用数码管显示时间
1. The timer function: including, minutes and seconds when the timing
2. The timing and alarm clock function: set time out according to the alarm
3. When the function of hours, minutes and: can manual adjustments to calibration second time
4. Strike on the function
5. Using digital pipe display time (2011-07-29, VHDL, 2KB, 下载4次)
数字钟的实现，包括报时，校时，清零，闹钟等功能，内附源文件电路图跟源代码。
This is a digital clock to achieve the VHDL. Using eight digital tube display!- Adjustable alarm can be school. (2011-06-15, VHDL, 90KB, 下载4次)
数字时钟，整点报时，有校分校时功能，底层用VHDL，顶层原理图
Digital clock, the whole point of time, when a school campus functions, the bottom with VHDL, top-level schematic (2012-01-05, VHDL, 4KB, 下载4次)
1、24小时计数显示；
2、具有校时功能（时，分） ；
3、实现闹钟功能（定时，闹响）；
1,24 hours counting display 2, with the school when the function (hour, minute) 3 to achieve alarm functions (timing, downtown ring) (2009-12-01, VHDL, 7KB, 下载4次)
自己写的数字闹钟含校时和闹钟设定,闹钟铃声为梁柱歌曲,
Write their own digital clock and alarm clock with school settings, the alarm tone for the column songs, (2008-07-12, VHDL, 7KB, 下载4次)
简易数字钟，包括时间显示时分秒各位的校时接口，输出BCD码
Simple digital clock, including the minutes and seconds time display when your school interface, the output BCD code (2009-01-02, VHDL, 45KB, 下载3次)
此程序是实现数字钟的，包括校时 闹钟 二十四小时和十二小时的转换
This procedure is to achieve digital clock, including the school alarm clock 24 hours and 12 hours the conversion (2008-12-25, VHDL, 563KB, 下载3次)
满足数字钟的一切功能，包括定时，整点报时，时分秒的校时，年月的显示
Digital clock to meet all of the features, including timing, the whole point of time, when every minute of school, the years of the show (2011-12-18, VHDL, 265KB, 下载3次)
数字钟的VHDL语言实现基本功能，包括
1、24小时计数显示；
2、具有校时功能（时，分） ；
附加要求：
1、实现闹钟功能（定时，闹响）；
Digital clock in the VHDL language for basic functions, including 1,24-hour count display 2, when a school function (hour, minute) additional requirements: 1, to achieve the alarm function (time, alarm sound) (2010-11-25, VHDL, 1KB, 下载3次)
(1)设计一个具有‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
(2)具有手动校时、校分的功能。
(3)闹钟功能，能在设定的时间发出提醒（绿色LED灯闪烁）。
(4)能进行整点报时。从59分50秒起，每隔2秒钟绿色LED灯闪一次，连续5次，达到整点时红色LED灯闪一次。
(1) design a ' when' , ' points' , ' s' decimal digital display (hour timer from 00 to 23). (2) having a manual correction, the correction sub functions. (3) The alarm clock function, can send reminders at a set time (green LED flashes). (4) The whole point timekeeping. Starting at 59 minutes and 50 seconds, every 2 seconds the green LED lights flash five times in a row, when the whole point of the red LED lights flash once. (2013-03-27, VHDL, 2KB, 下载3次)
电子表的设计包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块
module clock(clk,rst,clock_en,second,minute,hour)
input clk,rst,clock_en
output[5:0]second,minute,hour
reg[5:0]second,minute,hour
(2012-06-19, VHDL, 109KB, 下载3次)
本数字钟可实现正常计时，支持12小时和24小时两种计时方式的切换，允许用户手动调时和整点报时功能。
系统对外向用户提供了两个按键:功能键和调整键.功能键用于功能选择,调整键用于相关的时间调整. 当接通电源后系统便开始正常计时，如果按一下功能键，则进入调小时模式,再按一次则进入调分模式,再按则进入12/24小时模式选择设定,再按则恢复到正常计时状态. 在正常计时状态下，用户可以选择12或24小时的计时方式，第六个数码管的右下方小点亮表示是12小时模式，不亮表示24小时。整点报时时，六个数码管的小点会同时亮。
当用户通过按键进入校时状态时，第二个数码管的小点变亮，表示现在在对小时进行设置；同样，进行校分状态时，第四个数码管的小点会亮，表示现在正在对分钟进行设置。
The digital clock can achieve normal timing, support for 12 hours and 24 hours two timing mode switch allows the user to manually tune and the whole hour. Systems external to provide users with two keys: the function key and adjust the key function keys for function selection and adjustment button for the relevant time to adjust the power system began timing, if you click a function key, adjust the hour mode, and then once for the tone patterns, and then enter 12/24 hour mode select Settings, and then restored to normal timekeeping. in normal time status, the user can select 12 or 24 hours timing sixth of the way, the bottom right of the small digital tube light 12 hour mode, light 24 hours. The whole point of time when the dot of six digital tube light. Button to enter the school when the second digital tube light, that now the hour set Similarly, when the school sub-state, the fourth digital control points will be bright, said that now are minute set. (2012-05-25, VHDL, 17KB, 下载3次)
设计一台能显示时、分、秒的数字电子钟，具体要求如下：
（1）时计数器用24进制计时电路，分、秒计数器用60进制计分、计秒电路；
（2）可手动校时，能分别进行时、分的校正；
（3）能实现整点报时功能。
Design a table can display hours, minutes and seconds of digital electronic clock, the specific requirements are as follows: (a) when the counter with 24 hexadecimal timing circuits, minutes, seconds counter with 60 decimal points, namely, second circuit (2) may be Manually school, be able to separate hours, minutes correction (3) to achieve the whole point timekeeping function. (2013-06-23, VHDL, 913KB, 下载3次)