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[Windows编程] timesystem

数电实验 设计并实现一个学校作息时间管理系统 有常态、考试和假日三种工作模式,利用点阵显示。可以进行校时.里面包括各分程序和最后的FINAL总程序,以及报告和实验说明。
Number of electric experimental design and implement a school management system has normal schedule, examinations and holidays three operating modes, using the dot display. When can the school. Which includes the sub-program and final FINAL total program, as well as reports and experiments. (2014-12-15, VHDL, 4320KB, 下载3次)

http://www.pudn.com/Download/item/id/2674569.html

[单片机开发] clock

多功能数字钟,具有调时校时,整点报时,闹铃及其设定等功能,可直接下载到DE0开发板上
verilog clock (2014-10-29, VHDL, 177KB, 下载3次)

http://www.pudn.com/Download/item/id/2644472.html

[VHDL/FPGA/Verilog] zhong

数字钟,实现整点报时以及校时功能,烟大数字逻辑课程实验。
Digital clock, realize the whole point timekeeping and school function, smoke large digital logic course experiment. (2013-11-08, VHDL, 496KB, 下载3次)

http://www.pudn.com/Download/item/id/2395360.html

[VHDL/FPGA/Verilog] duogongnengshuzibiao

多功能数字电子表 (1)正常计时:秒(60)、分(60)、小时(24)计数;秒计时的频率为1Hz,数码管用动态扫描实时显示计时的小时、分、秒。 (2)整点报时:逢整点蜂鸣器在“59”分钟的第51、53、55、57秒发频率为512Hz的低音,在“59”分钟的第59秒发频率为1024Hz的高音。 (3)校时: 校小时, 显示小时数码管以4Hz的频率递增计数; 校分, 显示分数码管以4Hz的频率递增计数; 校秒, 秒清0。 其他: 1.晶振为12 MHz 2. 采用CPLD 器件为ALTERA 的EPM7064SL-44 3.采用数码管显示
Multifunction digital electronic watch (1) normal time: second (60), points (60), hours (24) counts second timing frequency of 1Hz, dynamic scanning real-time display of digital works timekeeping hour, minutes and seconds. (2) The whole point timekeeping: Every whole point of the buzzer in the " 59" minutes of 51,53,55,57 second frequency is 512Hz bass made in the " 59" minutes of the first 59 seconds made the treble frequency is 1024Hz . (3) school: school hours, hours of digital tube display frequency of 4Hz counts school hours, the display of digital 4Hz for counting school, seconds cleared. Others: 1. Crystal is 12 MHz 2. Using ALTERA CPLD device as the EPM7064SL-44 3. Using digital display (2013-08-20, VHDL, 503KB, 下载3次)

http://www.pudn.com/Download/item/id/2335318.html

[VHDL/FPGA/Verilog] shuzidianzizhong

基于VHDL基于VHDL数字电子钟设计(时、分、秒),有校时,分频,倒计时流水灯灯功能。
Based on VHDL VHDL-based design of digital electronic clock (hours, minutes, seconds), there is the school, the frequency, the countdown water lights lamp function. (2012-01-04, VHDL, 2KB, 下载3次)

http://www.pudn.com/Download/item/id/1749904.html

[VHDL/FPGA/Verilog] clock

基于vhdl的数字钟,分别由6个数码管显示24小时、60分钟、60秒的计数显示;设有校时、校分、秒清零校正功能,分别由3个按键控制;验证可用。
On vhdl digital clock, respectively, by 6 digital tube display 24 hours, 60 minutes, 60 seconds of the count display with school hours, school hours, seconds, cleared correction function, respectively, by three buttons control verification is available. (2009-11-13, VHDL, 261KB, 下载3次)

http://www.pudn.com/Download/item/id/969255.html

[VHDL/FPGA/Verilog] shuzizhong

1.计时功能采用24小时方式,显示小时、分钟、秒。 2.采用双键校时法,MODE和SET,前者选择始终模式(包括小时、分、秒校时),后者校时脉冲。 3.结果用6个共阳数码管显示。
1. Time functions the way the 24-hour, show hours, minutes, seconds. 2. The use of double bond at the Law School, MODE and SET, always choose the former model (including the hours, minutes and seconds when the school), the latter pulse school. 3. Results A total of six positive digital display. (2009-07-27, VHDL, 318KB, 下载3次)

http://www.pudn.com/Download/item/id/857701.html

[Windows编程] sun_clock

能手动校时,整点报时的时钟,具有闹钟功能,在实验中测试成功
Can manually school, the whole point of clock time, with alarm clock function, in experiments to test the success of (2009-06-01, VHDL, 408KB, 下载2次)

http://www.pudn.com/Download/item/id/787302.html

[汇编语言] clk

设计一个简易数字钟,具有校时功能: 1、以至少6位LED数码管显示时、分、秒,时为24进制。 2、采用最多8个键实现校时功能。
The design of a simple digital clock with a school function: 1, to at least six LED digital display hours, minutes and seconds, time for the 24-band. 2, using up to eight key functions to achieve school. (2008-12-24, VHDL, 59KB, 下载2次)

http://www.pudn.com/Download/item/id/614840.html

[其他] watch

功能更强大的数字时钟,有年份,月,日,时,分,秒和星期,可以调校
More powerful digital clock, there are years, months, days, hours, minutes, seconds and weeks, you can adjust the (2008-11-05, VHDL, 3KB, 下载2次)

http://www.pudn.com/Download/item/id/573412.html

[VHDL/FPGA/Verilog] kuaijintuiyinyueshizhong_VHDL

本程序为模拟可校时的时钟程序;clk--时钟信号,rst--清零信号,set_en--校时 使能信号,faster--快进信号,slower--快退信号,hour--小时校时,min--分钟校 时,(hh,hl,ml,mh,sh,sl)--时,分,秒显示信号。 校时的时候,秒清零。 (2008-05-02, VHDL, 110KB, 下载2次)

http://www.pudn.com/Download/item/id/450976.html

[Windows编程] clock

实现一个能显示小时、分钟、秒的多功能时钟,具有整点报时、闹钟、手动校时功能。
To achieve a can display hours, minutes, seconds, multi-functional clock, with the whole point timekeeping, alarm clock, manual, when the school functions. (2009-10-08, VHDL, 76KB, 下载2次)

http://www.pudn.com/Download/item/id/931396.html

[单片机开发] CLKGDF

设计了一个数字钟,可以完成00:00:00到23:59:59的计时功能,并在控制电路的作用下具有保持、清零、快速校时、快速校分、整点报时等功能。
Design a digital clock, timing functions can be completed from 00:00:00 to 23:59:59, and has to maintain the role of the control circuit is cleared quickly School, rapid correction points, the whole point timekeeping function. (2013-04-10, VHDL, 178KB, 下载2次)

http://www.pudn.com/Download/item/id/2194775.html

[VHDL/FPGA/Verilog] VHDL

数字时钟,实现24小时数码管显示,可以实现按键校时
Digital clock, 24 hours to achieve digital display, you can achieve the key school (2016-06-17, VHDL, 1789KB, 下载2次)

http://www.pudn.com/Download/item/id/1466148530233861.html

[VHDL/FPGA/Verilog] jiandanshuzizhong

数字钟;可以实现校时、走时、单独计时以及闹钟功能。
Digital clock can be achieved when the school, while walking alone timekeeping and alarm function. (2016-05-21, VHDL, 432KB, 下载2次)

http://www.pudn.com/Download/item/id/1463830034197095.html

[VHDL/FPGA/Verilog] Digital-Clock

信号定义: clk: 标准时钟信号,本例中,其频率为4Hz; clk_1k: 产生闹铃音、报时音的时钟信号,本例中其频率为1024Hz; mode: 功能控制信号; 为0:计时功能; 为1:闹钟功能; 为2:手动校时功能; turn: 接按键,在手动校时功能时,选择是调整小时,还是分钟; 若长时间按住该键,还可使秒信号清零,用于精确调时; change: 接按键,手动调整时,每按一次,计数器加1; 如果长按,则连续快速加1,用于快速调时和定时; hour,min,sec:此三信号分别输出并显示时、分、秒信号, 皆采用BCD码计数,分别驱动6个数码管显示时间; alert: 输出到扬声器的信号,用于产生闹铃音和报时音; 闹铃音为持续20秒的急促的“嘀嘀嘀”音,若按住“change”键, 则可屏蔽该音;整点报时音为“嘀嘀嘀嘀—嘟”四短一长音; LD_alert: 接发光二极管,指示是否设置了闹钟功能; LD_hour: 接发光二极管,指示当前调整的是小时信号; LD_min: 接发光二极管,指示当前调整的是分钟信号。
Signal definition: clk: standard clock signal, in this case, the frequency of 4Hz clk_1k: generating an alarm sound, the sound of the chime of the clock signal, in this case a frequency of 1024Hz mode: function control signal to 0: timing functions 1: alarm clock function 2: Manual calibration function turn: take the keys, function in the manual when school choice is to adjust the hours, or minutes if long press the button, but also to second signal cleared for precise time-setting change: access key, manually adjust the time, every time you press, the counter is incremented if long press, then in quick succession by 1, when used to quickly tune and timing hour, min, sec: The three signals are output and display hours, minutes, seconds signal using BCD code are counted separately driven six digital tube display time alert: a signal output to the speaker for generating an alarm tone chime tone alarm tone sustained 20 seconds of rapid " Didi tick" sound, if the hol (2015-12-09, VHDL, 16KB, 下载2次)

http://www.pudn.com/Download/item/id/1449667403301500.html

[单片机开发] Digital-Clock

1.具有‘时’、‘分’、‘秒’、‘毫秒’的数码管十进制数字显示。 2. 具有手动校时、校分的功能。 3.具有定时与闹钟功能,能在设定的时间使LED灯亮光。 4.能进行整点报时。即从59分50秒起,每隔2秒钟绿色LED灯点亮一次,连续5次,最后一次红色LED灯点亮一次,表明到达整点。 5、具有秒表功能,能显示1 秒,手动停止。 6、具有倒计时功能,显示小时、分钟、秒。
1. With ' when' , ' points' , ' second' , ' ms' digital tube display decimal digits. (2) When a manual school, school of function. 3. With a timer and alarm clock function, can make the LED lights light at a set time. 4. Can carry the whole point timekeeping. Namely, from 59 minutes and 50 seconds, every 2 seconds the green LED lights up once, five consecutive times, the last time the red LED lights up, indicating that reaches the whole point. 5, with a stopwatch function that can display one percent second manually stopped. 6, with a countdown function, display of hours, minutes, seconds. (2014-03-10, VHDL, 2KB, 下载2次)

http://www.pudn.com/Download/item/id/2480038.html

[VHDL/FPGA/Verilog] shuzizhong

数字钟,校时较分,显示,用元件例化写的vhdl文件,两个24进制,1个60进制计数器
Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter (2014-03-03, VHDL, 457KB, 下载2次)

http://www.pudn.com/Download/item/id/2474339.html

[VHDL/FPGA/Verilog] 25

电子钟(模式转换24/12进制,校时,校分)
Clock (24/12 hex mode conversion, school hours, school hours) (2010-07-09, VHDL, 102KB, 下载2次)

http://www.pudn.com/Download/item/id/1236670.html

[单片机开发] Applicationof8031controlleddigitalclock

应用8031单片机控制的数字时钟上,在设计上采用硬件计数与软件计数相结合的方式,并且定时器T0采用了中断方式,优先级最高。然后通过开关的闭合与关断来控制闹钟的校时,整点报时等功能。
Application of 8031 controlled digital clock, counting in the design of hardware and software using a combination of counts and using the timer interrupt T0, the highest priority. Then closed through the switch to control the clock and off the school, the whole point of time and other functions. (2010-12-14, VHDL, 862KB, 下载1次)

http://www.pudn.com/Download/item/id/1379764.html
总计:129