基于verilog简单数字时钟程序，可实现校时，校分功能
Based verilog simple digital clock procedures, can be achieved when the school, school division function (2016-07-03, VHDL, 1128KB, 下载1次)
显示时、分、秒，有手动校时功能，计时过程具有报时功能
Display hours, minutes, seconds, manual timing function, timing processes with chime (2016-03-26, VHDL, 13KB, 下载1次)
采用 6 个数码管分别显示小时、分钟和秒的数值；
(2) 计时方式可在 12 小时/24 小时之间切换；
(3) 通过按键可以对 “时”和 “分”进行校时，同时秒计数器清零。
Using six digital tube display hours, minutes and seconds values
(2) the timing mode can be between 12 hours/24 hours switch
(3) may be on the when and points in the school through the key, while the second counter is cleared. (2014-12-08, VHDL, 530KB, 下载1次)
数字时钟 LCD1602显示 可以校时。
编译环境QUARTUS II 7.2
Digital clock LCD1602 display can be corrected.
Compilation environment QUARTUS II 7.2
(2014-06-27, VHDL, 2107KB, 下载1次)
数字电子钟的设计，振荡器产生稳定的高频脉冲信号,作为数字钟的时间基准,然后经过分频器输出标准秒脉冲。秒计数器满60后向分计数器进位,分计数器满60后向小时计数器进位,小时计数器按照“24翻1”规律计数。计数器的输出分别经译码器送显示器显示。计时出现误差时,可以用校时电路校时、校分。
Digital electronic clock design, stable high frequency oscillator generates a pulse signal as a digital clock time reference, and then passes through a divider output standard second pulse. Second counter at least 60 minutes after the binary counter, minute counter at least 60 hours after the binary counter, hour counter in accordance with the "24 turn a" regular count. The outputs of the counter is sent to the decoded display. Timing errors, you can use the circuit when the school when the school, school hours.
(2013-07-02, VHDL, 1469KB, 下载1次)
UFSC语言和硬件描述课程知识库，Araranguá校区。，
Repository for the Language and Hardware Description course at UFSC, Araranguá campus., (2023-03-02, VHDL, 0KB, 下载0次)
在quarters ii上连接alter公司开发板实现的数字钟，可以手动校时校分。
Connect the digital clock implemented by alter development board on quarters ii, and it can proofread the time manually. (2019-04-10, VHDL, 2980KB, 下载0次)
（1）正常计时：秒（60）、分（60）、小时（24）计数；秒计时的频率为1Hz，数码管用动态扫描实时显示计时的小时、分、秒。
（２）整点报时：逢整点蜂鸣器在“59”分钟的第51、53、55、57秒发频率为500Hz的低音，在“59”分钟的第59秒发频率为1000Hz的高音。
（３）校时：
校小时, 显示小时数码管以4Hz的频率递增计数；
校分, 显示分数码管以4Hz的频率递增计数；
校秒, 秒清0。
(1) normal time: second (60), sub (60), hour (24) count; the frequency of second time is 1Hz, the digital tube dynamic scan real-time display time, minute, second.
(2) whole point: a buzzer with a frequency of 500Hz in fifty-first, fifty-third, fifty-fifth and 57 seconds of the "59" minute, and the frequency of 1000Hz in the fifty-ninth seconds of "59" minutes.
(3) school:
The hour is displayed, and the number of the hour digital tube is increased with the frequency of 4Hz.
The score is displayed, and the digit tube is increased by counting the frequency of 4Hz.
School seconds, second clear 0. (2018-07-04, VHDL, 46KB, 下载0次)
用FPGA实现闹钟，校时，计时功能，基于quartus II
Realization of alarm clock, school time, time function (2018-05-12, VHDL, 4189KB, 下载0次)