神经网络：使用VHDL在FPGA中对人工神经网络进行硬件加速。
Innervator: Hardware Acceleration for Artificial Neural Networks in FPGA using VHDL. (2024-03-18, VHDL, 0KB, 下载0次)
在Arty A7 FPGA上开发的音效项目。
Sound Effects Project developed on Arty A7 FPGA. (2024-02-27, VHDL, 0KB, 下载0次)
布尔诺理工大学VHDL课程
VHDL course at Brno University of Technology (2024-01-06, VHDL, 0KB, 下载0次)
Arty A7 100T FPGA开发板上的SoomRV
SoomRV on the Arty A7 100T FPGA dev board (2023-11-22, VHDL, 0KB, 下载0次)
这是我使用Digilent.的ARTY A7 35T开发板实现的采样器。，
This is my implementation of a Sampler using the ARTY A7 35T developement board by Digilent., (2022-04-15, VHDL, 0KB, 下载0次)
97-98第一学期VLSI，Jahanian博士，
97-98 first semester VLSI by Dr. Jahanian, (2019-01-01, VHDL, 0KB, 下载0次)
Keerthan Nayak，Ryan Fallis，Richard的ECE 540 SOC设计最终项目，
ECE 540 SOC design final project by Keerthan Nayak, Ryan Fallis, Richard, (2022-01-03, VHDL, 0KB, 下载0次)
创建一个使用brainf*ck语言作为操作码的处理器的vhdl实验，
A vhdl experiment of creating a processor that uses the brainf*ck language as its opcodes, (2023-07-30, VHDL, 0KB, 下载0次)
基于张量流的轻量级ECG CNN分类器的开发及其在CMOD A7 FPGA上的实现
Lightweight ECG CNN classifier developed with tensorflow and implemented on CMOD A7 FPGA for edge computing (2022-07-26, VHDL, 69600KB, 下载0次)
用于Xilinx FPGA的Hastlayer硬件侧组件。有关详细信息，请参阅<https://hastlayer.com>。
用于Xilinx FPGA的Hastlayer硬件侧组件。有关详细信息，请参阅<https://hastlayer.com>。 (2022-10-09, VHDL, 751KB, 下载0次)
GRLIB GPL支持Digilent CMOD A7 35T板
GRLIB GPL support for Digilent CMOD A7 35T board (2020-01-05, VHDL, 2651KB, 下载0次)
用于VHDL的GNSS代码和信号生成。GPS（L1 C A、L5）、伽利略（E1OS、E5）。包括Xilinx ISE测试台和wa...
GNSS codes and signal generation for VHDL. GPS (L1 C/A, L5), Galileo (E1OS, E5). Includes Xilinx ISE testbench and wave configuration files. (2018-01-03, VHDL, 88KB, 下载0次)
VHDL代码，用于生成GPS L1 C A和Galileo E1OS和E5 PRN以及无数据信号。不包括辅助代码。
VHDL codes to generate GPS L1 C A and Galileo E1OS and E5 PRNs and dataless signals. Secondary codes not included. (2019-02-22, VHDL, 782KB, 下载0次)
MRISC32 ISA的流水线有序标量VHDL实现
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA (2023-03-30, VHDL, 293KB, 下载0次)
一种基于MRISC32-A1 CPU的计算机（FPGA SoC）
A computer (FPGA SoC) based on the MRISC32-A1 CPU (2023-03-30, VHDL, 385KB, 下载0次)
布尔诺理工大学VHDL课程
VHDL course at Brno University of Technology (2023-05-07, VHDL, 10263KB, 下载0次)
用于测试IIC传感器的温度和相对湿度读数的不同实现方式的小型FPGA项目
A small FPGA project of different implementations for testing Temperature and Relative Humidity readings of a IIC sensor (2023-04-30, VHDL, 70588KB, 下载0次)
（您自己的数字加速器）通过使用有限脉冲响应（FIR）和低通滤波器（LPF...
(Your Own Digital Accelerator) A Smoothing filter by using a Finite Impulse Response (FIR) and a Low Pass Filter (LPF) algorithm. The hardware used is a NEXYS A7 Field Programmable Gate Array (FPGA) programmedin Verilog. (2020-07-25, VHDL, 13044KB, 下载0次)
ZX Spectrum的端口Digilent Nexys A7-100T板的下一个核心。
Port of the ZX Spectrum Next core to the Digilent Nexys A7-100T board. (2022-03-16, VHDL, 113226KB, 下载0次)
這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸
This is a DWT of the Verilog code, its main function is between the PC and FPGA communication DWT procedures and transmission (2008-03-28, VHDL, 1433KB, 下载282次)