艺术品A7 I2C MPU 6050
ARTY A7 I2C MPU 6050 (2024-01-02, Verilog, 0KB, 下载0次)
这是一个包含基于ARM-Cortex-M0的SOC设计的回购，在Nexus-4-DDR、Nexus-4和ARTY-A7 FPGA平台上实现。，
This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms., (2023-09-06, Verilog, 0KB, 下载0次)
RISC-V 5级流水线RV32I实现，在verilog中转发，具有在xilinx nexus a7 FPGA上工作的驱动程序...
RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards (2022-08-22, Verilog, 1156KB, 下载0次)
在Nexys 4 DDR Nexys A7 FPGA训练器上使用DDR2内存和MIG IP的示例
Example using DDR2 memory and MIG IP on the Nexys 4 DDR Nexys A7 FPGA Trainer (2022-06-07, Verilog, 5090KB, 下载0次)
njtech数字设计。基于Nexys A7 100T的fpga数字报警系统
njtech digital design. a fpga digital alarm system with Nexys A7 100T (2019-06-11, Verilog, 2613KB, 下载0次)
这个项目的目的是模仿一个篮球记分板，有计时器和两个团队的得分。请参阅pi的自述文件...
Objective of this project was to emulate a Basketball score board, with timer and two teams scores. See readme for pic and more details. Release published v1.0.5 (2023-05-29, Verilog, 2216KB, 下载0次)
使用gtp进行收发sdi的demo工程，实测能用，欢迎下载 (2023-01-11, Verilog, 138KB, 下载0次)
http://www.pudn.com/Download/item/id/1673434140147193.html
Xilinx-A7开发板手册，希望对大家有帮助
Xilinx-A7 development board manual (2021-03-13, Verilog, 2025KB, 下载0次)
利用FPGA通过SPI接口配置SONY IMX264图像传感器，按照全画幅输出图像。XILINX A7平台实测
Using FPGA to config SONY IMX264 CMOS image sensor through SPI interface (2019-12-05, Verilog, 3KB, 下载14次)
本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出
In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output (2019-05-06, Verilog, 15402KB, 下载3次)
用于XILINX的A7平台的DDR3控制器接口，包括分时读写控制，供参考学习
XILINX A7-series DDR3 control unit interface (2019-04-21, Verilog, 4KB, 下载3次)
useful cmod a7 constraints file
useful cmod a7 constraints file (2018-12-15, Verilog, 236KB, 下载0次)
128×160规格TFT显示屏显示图片的源代码
128 x 160 specifications TFT display picture of the source code (2018-08-18, Verilog, 6586KB, 下载3次)
包含EGO开发的所有资料，有注意事项，约束文件，上手指南，硬件手册等。
Contains all the information developed by EGO, notes, constraints, Handbook, hardware manuals and so on. (2018-05-06, Verilog, 4777KB, 下载14次)
基于verilog编写的MSK调制程序，modsim仿真波形正确
Verilog based MSK modulation program written, modsim simulation waveform correct (2018-04-26, Verilog, 1059KB, 下载26次)
xilinx FPGA A7 驱动DDR3的DEMO例程
DEMO routines driven by Xilinx FPGA A7 for DDR3 (2018-04-13, Verilog, 23789KB, 下载14次)
VERILOG编程指导书，针对于vivado编程应用
VERILOG programming guide for the application of vivado programming (2017-12-17, Verilog, 3182KB, 下载8次)
crc16——128bit的报文检验模块，验证报文是否正确
ata[112],data[113],data[114],data[115],data[116],data[117],data[118],data[119],
data[104],data[105],data[106],data[107],data[108],data[109],data[110],data[111],
data[96],data[97],data[98],data[99],data[100],data[101],data[102],data[103],
data[88],data[89],data[90],data[91],data[92],data[93],data[94],data[95],
data[80],data[81],data[82],data[83],data[84],data[85],data[86],data[87], (2017-08-31, Verilog, 1KB, 下载3次)
自己编写的1553b总线的曼切斯特编码和解码电路
1553b encoder and decoder (2017-08-23, Verilog, 99KB, 下载13次)
用于测试FPGA串口接收，带singelTap。便于观测。
Used to test the FPGA serial port reception, with singelTap. Convenient observation. (2017-07-28, Verilog, 6463KB, 下载1次)