使用直接数字合成的简单波形发生器，用作AXI Lite IP，
A simple waveform generator using Direct Digital Synthesis, working as an AXI Lite IP, (2020-01-02, Verilog, 0KB, 下载0次)
使用verilog语言，实现dds信号发生器的源代码
use dds to generate chirp signal (2021-04-19, Verilog, 4206KB, 下载0次)
DDS的基本原理主要由五部分组成，分别是；相位累加器，正弦波形存储器，数模转换器，低通滤波器和时钟，将相位累加器输出的数据作为地址，用来查询表的数据，将取出的正弦数据通过数模转换器输出模拟信号，模拟信号再通过一个低通滤波器输出纯净的正弦波信号。
The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal. (2020-09-16, Verilog, 2407KB, 下载2次)
DDS信号发生器的实现
本工程实现DDS直接数字式频率合成器，它主要由3部分组成：相位累加器，相位幅度转换，数模转换器（DAC）。相位累加器的高10比特用于ROM的索引地址。
Realization of DDS signal generator (2020-08-24, Verilog, 285KB, 下载1次)
基于FPGA的任意波形发生器DDS,verilog编写，正常使用
Arbitrary waveform generator DDS based on FPGA (2020-06-09, Verilog, 11624KB, 下载6次)
基于DDS设计的函数发生器，可以产生正弦波、方波、三角波和锯齿波，其中所有波形的频率和幅度均可变，方波的占空比可以独立调节，并且可以通过串口实现这些改变。
The function generator based on DDS can produce sine wave, square wave, triangle wave and sawtooth wave, in which the frequency and amplitude of all waveforms can be changed, the duty cycle of square wave can be adjusted independently, and these changes can be realized through serial port. (2020-01-10, Verilog, 13KB, 下载4次)
dds信号发生器，可产生正弦信号。锯齿波，梯形波
DDS signal generator can produce sinusoidal signal. Sawtooth wave, trapezoidal wave (2019-03-23, Verilog, 3342KB, 下载7次)
FPGA测序和DDS产生各种波形程序，用Atral器件开发
FPGA sequencing and DDS generate various waveform programs. (2018-11-14, Verilog, 6563KB, 下载2次)
基于fpga的信号发生器，使用dds 频率合成生成多种波形
FPGA based signal generator, using DDS frequency synthesis to generate multiple waveforms. (2018-11-14, Verilog, 6241KB, 下载6次)
fpga,塞林斯IP核应用。介绍波形发生器的应用。编辑方法，功能，参数。
The Xilinx LogiCORE IP Direct Digital Synthesizer (DDS) Compiler core implements high performance, optimized Phase Generation and Phase to Sinusoid circuits with AXI4-Stream compliant interfaces. (2018-06-21, Verilog, 895KB, 下载14次)
基于FPGA的DDS相位累加器，连接至存有波形数据的rom后再接至DA可以输出对应的波形
abcdefghijklmnopqrstuvwxyz (2018-05-10, Verilog, 76KB, 下载6次)
基于fpga实现信号发生器，本设计采用方法为基于dds原理产生正线波信号输出。
DDS wave signal output line. (2018-04-03, Verilog, 2599KB, 下载2次)
DDS技术实现波形产生代码，可以编译下载学习使用！
DDS generate diagram program (2018-03-04, Verilog, 4870KB, 下载1次)
可以产生数字波形信号，频率可调，相位可调
Can produce the digital waveform signal, the frequency is adjustable, the phase is adjustable (2017-12-03, Verilog, 458KB, 下载4次)
描述了verilog实现的DDS信号发生器，可以经过FPGA验证，包括了代码实现以及书写。代码可以经过altera的EDA工具进行了验证，可以实现信号发生器的基本功能。希望大家珍惜，并好好学习。
Describes the Verilog implementation of the DDS signal generator, which can be verified by FPGA, including code implementation and writing. Code can be verified by the Altera EDA tool, you can achieve the basic functions of the signal generator. I hope you will cherish and study well. (2017-09-12, Verilog, 102KB, 下载12次)
用verilog语言，在fpga上实现dds信号发生器，并在vga上显示出来
Verilog realizes DDS Signal Generator (2017-09-07, Verilog, 38377KB, 下载13次)
四通道DDS信号发生器，很好用的代码，大家一起分享
Four-channel DDS signal generator (2017-08-11, Verilog, 6633KB, 下载11次)
用FPGA实现的DDS，用法简单，波形稳定
DDS is implemented using FPGA (2017-08-01, Verilog, 1931KB, 下载2次)
DDS波形生成器verilog语言书写（FPGA型号cy4以上）
DDS generate verilog (2017-07-17, Verilog, 386KB, 下载33次)
基于DDS的信号发生器设计。DDS,FPGA,Verilog。
Design of signal generator based on DDS.DDS,FPGA,Verilog. (2017-07-11, Verilog, 10766KB, 下载2次)