rl02-01-磁盘模拟器-读卡器-克隆器-(写入器),
rl02-01-disk-emulator-reader-cloner-(writer), (2023-03-09, Verilog, 0KB, 下载0次)
mips处理器和存储器,
mips processor and memory, (2010-03-02, Verilog, 0KB, 下载0次)
纳米Risc处理器、显示器控制器、多功能显示器。。。
Processador nano-Risc, controlaor de display, e muito mais... (2022-04-02, Verilog, 2291KB, 下载0次)
sdram控制器,verilog语言编写 (2022-12-09, Verilog, 13KB, 下载0次)
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Design of shift add multiplier (2019-10-22, Verilog, 2KB, 下载0次)
16位补码,并行加法器(含减法器)Verilog及仿真
16-bit complement parallel adder (including subtractor) (2019-08-20, Verilog, 1333KB, 下载2次)
寄存器:4位双向移位寄存器74194,应用4位双向移位寄存器74194实现寄存器功能。
Register: 4-bit bi-directional shift register 74194, the application of 4-bit bi-directional shift register 74194 register function. (2019-06-21, Verilog, 2995KB, 下载0次)
多级CIC滤波器的代码,可直接运行,有注释
Multilevel CIC filter code, can be run directly, with notes (2018-10-10, Verilog, 3449KB, 下载5次)
基于D触发器时序电路,实现特定输入2进制序列的检测
Detection of specific input 2 binary sequence based on D flip flop sequential circuit (2018-07-12, Verilog, 1KB, 下载0次)
fpga,蜂鸣器,控制,程序,quartus ii
FPGA, buzzer, control, program, Quartus II (2018-05-23, Verilog, 720KB, 下载0次)
用Verilog语言编程实现4位BCD计数器的功能
Write the programm with Verilog language to implement the function of 4 - bit BCD counter. (2018-04-11, Verilog, 25KB, 下载14次)
在FPGA板子上的八种运算类型计算器,并有Error信息提醒。
Eight computing types calculators on the FPGA board and Error information reminders (2018-03-21, Verilog, 1033KB, 下载7次)
CAN 2.0协议控制器,非常全面的控制器Verilog代码,可靠通信,可放心使用。
CAN Bus 2.0 Controller. (2018-01-19, Verilog, 33KB, 下载24次)
器件EP4CE6F22C8N 4线-2线编码器 优先编码器
Device EP4CE6F22C8N lines to 4-2 encoder priority encoder (2018-01-16, Verilog, 71KB, 下载1次)
用verilog语言实现了一个计算器alu,实现加减乘除的简单计算。
Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide. (2017-12-22, Verilog, 1KB, 下载11次)
利用 fpga 实现约翰逊计数器的功能
fpga Realize the function of Johnson counter (2017-10-15, Verilog, 288KB, 下载1次)
多选一多路器,三人表决器,触发器,RS寄存器
Choose a road, three people vote, trigger, RS register (2017-09-12, Verilog, 26222KB, 下载3次)
MATLAB设计fir数字滤波器 , 结合modelsim软件仿真。
MATLAB design FIR digital filter (2017-08-23, Verilog, 918KB, 下载5次)
编码器计数,根据状态机原理,判断编码器所属状态。
Encoder count, according to the principle of the state machine, to determine the state of the encoder (2017-08-21, Verilog, 1KB, 下载3次)
10秒计数器模块VHDL源程序,在FPGA中实现计数器功能
10 seconds counter module VHDL source code, in FPGA realize counter function (2017-07-09, Verilog, 1284KB, 下载2次)