红外接收机、发射机和遥控器的编码器和解码器模块，
Encoder and decoder modules for infrared receivers, transmitters and remotes, (2023-08-03, Verilog, 0KB, 下载0次)
高性能动态存储器控制器，
High Performance Dynamic Memory Controller, (2014-07-17, Verilog, 0KB, 下载0次)
用于CNN加速器的DMA控制器，
DMA controller for CNN accelerator, (2017-05-22, Verilog, 0KB, 下载0次)
基本设计、带ALU的流水线CPU、第三版除法器、桶移位器、HiLo寄存器、多路复用器等。，
Design basic、Pipelined CPU with ALU, third edition divider, Barrel Shifter, and HiLo register, Multiplexer and so on., (2020-09-26, Verilog, 0KB, 下载0次)
MIPS处理器、BNN加速器、AXI4接口、缓存控制器和LRU更换，
MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement, (2022-11-04, Verilog, 0KB, 下载0次)
使用Verilog编写的计数器，能够实现计数功能
Counter,counting function (2020-11-25, Verilog, 69KB, 下载0次)
计数器是由基本的计数单元和一些控制门所组成，计数单元则由一系列具有存储信息功能的各类触发器构成，这些触发器有RS触发器、T触发器、D触发器及JK触发器等。
本代码在fpga中实现累加器的功能
The counter is composed of a basic counting unit and some control gates, while the counting unit is composed of a series of triggers with the function of storing information. These triggers include RS trigger, t trigger, D trigger and JK Trigger.
This code realizes the function of accumulator in FPGA (2020-09-16, Verilog, 1412KB, 下载0次)
用Verilog HDL语言写的模60计数器，可以自己随意修改模值，改为任意模值计数器
Module 60 counter.You can modify the module value at random and change it to any modulus counter. (2020-05-17, Verilog, 1KB, 下载0次)
一款verilog设计的SRAM控制器，可以实现AHB总线控制的功能。
abcdefghijklmnopqrstuvwxyz (2019-08-10, Verilog, 3300KB, 下载32次)
半加器实现，简单的半加器，作为新手实验用
Semi-adder implementation, simple semi-adder, as a novice experiment (2019-06-12, Verilog, 2960KB, 下载6次)
用VIVADO实现最简单的分频器，分成了三个频率
Using VIVADO to realize the simplest frequency divider, which is divided into three frequencies (2019-04-17, Verilog, 473KB, 下载1次)
EDA课程设计实现的模可变减法器，实现模可切换的计数功能。
The modular variable subtracting device implements the counting function of module switchable. (2018-07-06, Verilog, 3635KB, 下载1次)
移位寄存器模块用于存储串行输入滤波器的数据；乘加计算模块用于fir计算
The shift register module is used to store data of serial input filter, and the multiplier calculation module is used for FIR calculation. (2018-06-30, Verilog, 1KB, 下载3次)
几个Verilog例程，包含寄存器、锁存器、触发器等。
Several Verilog routines include registers, latches, triggers, and so on. (2018-05-11, Verilog, 2812KB, 下载0次)
8-3优先编码器，在vivado中的项目，可直接打开.xpr，版本vivado2017.4
8-3encodervivado2017.4 (2018-05-02, Verilog, 113KB, 下载7次)
用Verilog语言编写程序实现8比特约翰逊计数器
Write a program in Verilog language to implement the 8 bit Johnson counter. (2018-04-11, Verilog, 10KB, 下载4次)
数控分频器的verilog代码在eda上实现
verilog for numerical control divider (2018-01-11, Verilog, 2796KB, 下载2次)
3阶cic滤波器，16位输出，32倍降采样处理
The 3 order CIC filter, 16 bit output, 32 fold down sampling processing (2017-11-07, Verilog, 1KB, 下载10次)
简单的硬件描述语言verilog语言描述的128进制计数器。
Simple hardware description Language Verilog language described 128 binary counter. (2017-10-19, Verilog, 1KB, 下载3次)
蜂鸣器开关实例，拨码开关SW3的ON和OFF状态对应
控制蜂鸣器响或不响。
Buzzer switch example, dial code switch SW3 ON and OFF state corresponding
Controls whether the buzzer sounds or does not sound. (2017-09-06, Verilog, 121KB, 下载1次)