通过Matlab HDL编码器实现FIR滤波器,
Implementing FIR filter via Matlab HDL Coder, (2016-11-07, Verilog, 0KB, 下载0次)
基于RISC-V处理器的OFDM加速器
An OFDM Accelerator for RISC-V based Processors (2021-05-16, Verilog, 229KB, 下载0次)
一个LED显示的简单计数器,通过一个转码器连接LEDA simple counter with LED display
A simple counter with LED display (2021-04-20, Verilog, 2890KB, 下载0次)
译码器将一个确定信号或对象的代码“翻译”出来,变换成对应的输出信号或另一种代码的逻辑电路。译码器大致分为变量译码、码制变换译码、显示译码等。在ASIC设计中,在存储器控制电路中,译码器通常将地址线翻译成字线的控制输入。
3-8译码器
3-8 decoder with enable signal EN (2020-05-06, Verilog, 72KB, 下载0次)
基于FIR设计的100阶数字滤波器,选择的矩形窗
100 - order digital filter based on FIR (2020-03-06, Verilog, 11KB, 下载1次)
38译码器的实现和testbench文件仿真(无引脚分配)
my3_8.v and my3_8 testbench (2019-12-31, Verilog, 3KB, 下载0次)
实现了4位半加器的verilog HDL代码
Implementation of Verilog code for 4-bit semi-adde (2019-06-10, Verilog, 252KB, 下载0次)
fpga中基于verilog的比较器代码
fpga comparator code (2019-02-27, Verilog, 199KB, 下载0次)
智力抢答器
可直接运行的基于windows开发的Verilog HDL语言,使用Vivado软件运行。
含五个子程序,实现智力抢答功能。
Intellectual responder (2018-11-05, Verilog, 609KB, 下载3次)
简单的路由器的rtl设计和仿真测试,包括自动对比
Simple router RTL design and simulation test, including automatic comparison. (2018-10-21, Verilog, 9KB, 下载8次)
ddr3控制器,可以仿真、自己编写码源进行写入和读出,并对读出数据进行记录,轻松验证控制器正确性
The DDR3 controller can simulate and write its own code source to write and read out, and record the readout data, so as to verify the correctness of the controller. (2018-07-24, Verilog, 23875KB, 下载16次)
本实验主要是在FPGA上实现FIR数字滤波器的功能,不仅有工程文件,还具有论文资料。
This experiment mainly realizes the function of FIR digital filter on FPGA, not only has the engineering document, but also has the thesis information. (2018-05-21, Verilog, 13701KB, 下载16次)
单周期MIPS处理器的设计,附带测试文件。
The design of a single cycle MIPS processor comes with test files. (2018-04-25, Verilog, 1KB, 下载3次)
110的序列检测器,添加了使能端检查其正确性
The sequence detector of 110 adds the enable end to check its correctness. (2018-04-24, Verilog, 187KB, 下载4次)
基于FPGA的智力抢答器,基于Xilinx器件,包含主程序、仿真代码。
Intelligent answering machine based on FPGA (2018-04-17, Verilog, 3KB, 下载9次)
一个简单的timer,包括定时器,计数器功能模式,非常实用,供参考
A simple timer, including timer, counter function mode, very practical, for reference. (2018-02-08, Verilog, 1KB, 下载5次)
器件EP4CE6F22C8N 2-4译码器译码器
Device EP4CE6F22C8N 2-4 decoder decoder (2018-01-16, Verilog, 67KB, 下载1次)
该代码根据时序图,采用verilog代码实现了遥控器编码电路的功能。
The code according to the timing diagram, using Verilog code to achieve the function of the encoding circuit of the remote controller. (2017-11-27, Verilog, 127KB, 下载5次)
整个程序由心率传感器模块,体温传感器模块,3D计步器模块,FPGA开发板,A/D转换器,LCD显示屏等组成。
The entire program module by heart rate sensor, temperature sensor module, 3D pedometer module, FPGA development board, A/D converter, LCD display etc.. (2017-10-27, Verilog, 16840KB, 下载11次)
伺服电机主控制模块输入输出特性的简单模拟实现,输入目标电压及反馈的当前电压,输出对电机的控制脉冲波形
The simple simulation of the input and output characteristics of servo motor main control module, the input is target voltage and feedback is the current voltage, the output is the motor control pulse waveform (2017-07-25, Verilog, 2KB, 下载4次)