教育负载存储指令集体系结构处理器模拟器
Educational load store instruction set architecture processor simulator (2013-03-20, Verilog, 0KB, 下载0次)
用于旋风分离器V SoC的硬件MD5裂解器，
A Hardware MD5 Cracker for the Cyclone V SoC, (2015-03-25, Verilog, 0KB, 下载0次)
32位计时器计数器捕获软IP（Verilog），
A 32-bit Timer Counter Capture Soft IP (Verilog), (2023-08-16, Verilog, 0KB, 下载0次)
具有因子加速器的Piplined Extended MIPS处理器，
Piplined Extended MIPS Processor with Factorial Accelerator, (2019-12-12, Verilog, 0KB, 下载0次)
基于coolrunner2的基本pwm控制器led调光器
basic pwm controller led dimmer based on coolrunner 2 (2021-05-11, Verilog, 4KB, 下载0次)
带内存控制器的32位RISC-V处理器
32-bit RISC-V based processor with memory controler (2022-09-02, Verilog, 1838KB, 下载0次)
气泡分类器和奇偶换位分类器的Verilog实现。
Verilog implementation of Bubble Sorter and Odd Even Transposition Sorter. (2015-11-22, Verilog, 1314KB, 下载0次)
用于De0 Nano的Verilog uart接收器和发射器模块
Verilog uart receiver and transmitter modules for De0 Nano (2014-10-24, Verilog, 48KB, 下载0次)
将运算器模块与存储器模块进行连接.....................
Connect the arithmetic module with the memory module; (2020-06-29, Verilog, 210KB, 下载0次)
sdram控制器代码，实现sdram控制
SDRAM controller code to realize SDRAM control (2020-03-29, Verilog, 15297KB, 下载0次)
单总线接口master控制器，可综合可编译
onewire interface controller (2019-11-29, Verilog, 252KB, 下载0次)
用四個器段顯示器來完成0到9999的上數計數器
Using four segment displays to complete the up counter from 0 to 9999 (2019-11-08, Verilog, 3496KB, 下载0次)
提出了PLL中小数分频器实现的方法和建议，值得参考
the N-divider of PLL (2019-06-02, Verilog, 2330KB, 下载5次)
用Verilog设计一个比较器，实现对输入数字比较功能
Design a comparator with Verilog to realize the function of comparing input numbers (2018-12-03, Verilog, 409KB, 下载1次)
当定时器控制寄存器EX_CON的CNT_START信号为1时,32位定时器开始计数
ü 当计数值等于定时时间配置寄存器EX_TO,定时器变为0,此时定时器控制寄存
器EX_CON的INT_EN为1,OVFL_CLS信号为0时,定时器中断信号INT_B变为低
电平
ü 当定时器控制寄存器EX_CON的OVFL_CLS信号为1时,NT_B变为高电平
When the CNT_START signal of timer control register EX_CON is 1, the 32 bit timer starts counting.
U when the count value is equal to the time variable configuration register EX_TO, timer 0, timer control register at
When the INT_EN of the EX_CON is 1 and the OVFL_CLS signal is 0, the timer interrupt signal INT_B becomes low.
level
U OVFL_CLS signal when the timer control register EX_CON is 1, NT_B becomes high level (2018-04-10, Verilog, 1KB, 下载1次)
用Verilog HDL语言实现分频器，初学，简单
The realization of frequency divider in Verilog HDL,
Elementary learning is simple (2017-12-29, Verilog, 101KB, 下载1次)
实现线性寄存器的移位和反馈，通过FPGA开发板实现功能
The shift and feedback of the linear register are realized (2017-09-29, Verilog, 250KB, 下载3次)
使用verilog语言实现简单的DDR SDRAM控制器
Using Verilog language to achieve a simple DDR SDRAM controller (2017-08-10, Verilog, 1076KB, 下载4次)
verilog语言编写的硬件定时器，测试功能可用
Verilog yu yan bian xie de ying jian ding shi qi, qin ce gong neng ke yong (2017-08-04, Verilog, 3KB, 下载3次)
控制蜂鸣器让它有规律的发出声音，使得蜂鸣器发出 SOS 紧急救难信号
Control buzzer so that it regularly sounds, making the buzzer SOS emergency rescue signal (2017-07-18, Verilog, 152KB, 下载2次)