存储器控制器和与RISC V的集成，，
memory controller and integration with RISC V ,, (2023-10-24, Verilog, 0KB, 下载0次)
8b10b编码器和解码器（verilog）+测试台（systemverilog.）的源代码，
source code of the 8b10b encoder and decoder (verilog) + testbench (systemverilog), (2022-05-19, Verilog, 0KB, 下载1次)
在FPGA上实现梳妆滤波器的方案，包含滤波器原理实现方案，以及仿真图
The scheme for implementing a makeup filter on FPGA, including the filter principle implementation scheme and simulation diagram (2023-07-19, Verilog, 313KB, 下载2次)
用Verilog实现MIPS多周期处理器的数据路径和控制器，
Implementing Datapath and Controller of MIPS multicycle processor with Verilog, (2020-02-03, Verilog, 0KB, 下载0次)
一个完整的经典5级流水线MIPS 32位处理器，包括一个2位分支预测器、一个分支预测缓冲器和一个直接映射器...，
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache. (2019-09-03, Verilog, 0KB, 下载0次)
基于FPGA的I2C到RS-232串行转换器总线监视器
FPGA-based I2C to RS-232 serial converter bus monitor (2016-01-29, Verilog, 243KB, 下载0次)
基于verilog的双处理器缓存一致性缓存控制器
Cache controller based on verilog with cache coherence for two processors (2016-06-10, Verilog, 36KB, 下载0次)
Verilog中的流水线VGA文本字符生成器控制器
Pipelined VGA text character generator controller in Verilog (2018-12-08, Verilog, 944KB, 下载0次)
带有集成RS232调试器的Verilog I2C初始化器。
A Verilog I2C initializer with integrated RS232 debugger. (2022-08-19, Verilog, 27KB, 下载0次)
Turbo编码器中使用到的交织器的FPGA实现
Interleaver of Turbo encoder (2020-07-14, Verilog, 1KB, 下载10次)
木马触发器被插入微型UART内核的接收器部分中。Trojan计数器的时钟为系统时钟的负值，Trojan计数器的使能为16个内部信号的比较器。
Trojan triggers are inserted into the receiver section of the micro UART kernel. The clock of Trojan counter is the negative value of system clock, and the enable of Trojan counter is the comparator of 16 internal signals. (2020-02-28, Verilog, 59KB, 下载0次)
高速流水的SDRAM控制器，最高速度可达速度在200M左右
high speed SDRAM controller (2019-06-17, Verilog, 14562KB, 下载3次)
VHDL编写的，利用蜂鸣器实现播放乐曲的功能
using VHDL and making buzzle work (2019-06-09, Verilog, 3369KB, 下载2次)
一种同步器的FPGA表示，采用二级k触发器实现同步器的功能
A kind of synchronizer is represented by FPGA. The function of synchronizer is realized by two-stage k-flip-flop. (2019-04-18, Verilog, 129KB, 下载0次)
nor flash控制器接口，实测可用。
nor flash controller interface (2018-06-30, Verilog, 6KB, 下载7次)
SDRAM控制器，可控制SDRAM进行读写存储，含SDRAM控制器源码及SDRAM说明文档
SDRAM Controller have source code and spec (2018-05-09, Verilog, 758KB, 下载11次)
用EPM240F100C5实现74138译码器
Implementation of 74138 decoders with EPM240F100C5 (2018-04-16, Verilog, 147KB, 下载1次)
用verilog语言编写一个计数器，改参数实现不同时间的计数器
Writing a counter in the Verilog language (2018-02-28, Verilog, 381KB, 下载1次)
简单数字示波器的verilog设计,涉及到时钟同步，FIFO的配置和使用，非常适合用来学习FPGA以及熟悉quartus II 软件。
digital oscilloscope design (2017-11-28, Verilog, 4991KB, 下载3次)
用verilog语言实现数字电路低通滤波器
Implementation of digital circuit low-pass filter using Verilog language (2017-10-11, Verilog, 39KB, 下载24次)