控制器局域网协议在CC770控制器中的Verilog实现。，
Verilog Implementation of Controller Area Network protocol in CC770 controller., (2021-06-04, Verilog, 0KB, 下载0次)
音频和红外遥控pdm调制器和解调器的verilog实现，
verilog implement of pdm modulator and demodulator for audio and infrared remote, (2023-08-12, Verilog, 0KB, 下载0次)
在Spartan6 FPGA上合成的同步数据扰频器和解扰器，
synchronous data scrambler and descrambler synthesized on Spartan6 FPGA, (2021-01-04, Verilog, 0KB, 下载0次)
Verilog中的有刷直流电机PWM驱动器和正交转速计数器
Brushed DC motor PWM driver and quadrature tach counter in Verilog (2015-09-04, Verilog, 24KB, 下载0次)
Verilog Micron公司技术支持发给我的SDRAM控制器代码
SDRAM controller code from Verilog micron technical support (2020-06-29, Verilog, 291KB, 下载1次)
32位乱序处理器核硬件Verilog实现，双发射带Gshare预测器，6级流水线
out-of-order processor ridecore (2020-05-19, Verilog, 1127KB, 下载1次)
多摩川编码器的FPGA接口程序，已经在我公司的伺服驱动产品中应用。
The FPGA interface program of tamakawa encoder has been applied in the servo drive products of our company. (2020-04-19, Verilog, 15KB, 下载26次)
通过vivado实现38译码器，通过不同的输入实现相应的输出，低电平有效
The 38 decoder is realized by vivado, and the corresponding output is realized by different input. The low level is effective (2020-03-10, Verilog, 118KB, 下载6次)
伺服控制器的反馈信号进行处理，适用于增量编码器的位置处理
process the encoder signal of servo (2019-09-24, Verilog, 1KB, 下载0次)
SPI串行接口控制器，内含一个verilog代码和一个接口说明文档
SPI serial interface controller (2019-05-24, Verilog, 15KB, 下载5次)
：设计一个1MHz的FIR低通滤波器。
① 时钟信号频率16MHz;
② 输入信号位宽8bits，符号速率16MHz；
A 1MHz FIR low pass filter is designed.
(1) The clock signal frequency is 16MHz;
(2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz; (2019-05-19, Verilog, 51KB, 下载0次)
基础decoder，encoder，mux，priority encoder 代码以及testbench
basic decoder, encoder, mux, priority encoder code and testbench (2019-05-15, Verilog, 3378KB, 下载0次)
1. 利用一位半加器设计八位全加器
2. 进行功能仿真
1. Design of an eight-bit full adder by using a one-and-a-half adder
2. Functional simulation (2019-03-22, Verilog, 678KB, 下载0次)
36阶fir低通滤波器
附带仿真文件‘
可直接运行’
36 order FIR low pass filter
Incidental simulation file '
Can run directly ' (2018-06-12, Verilog, 7543KB, 下载11次)
产生相差90°的AB相脉冲，并且模拟AB相位的超前或滞后，用于ABZ编码器信号的分析
The AB phase pulse with a difference of 90 degrees is produced and the AB phase is simulated forward or lagging, for the analysis of the signal of the ABZ encoder (2018-01-03, Verilog, 5129KB, 下载13次)
fir滤波器源代码及测试程序,有限脉冲滤波器的源程序及测试程序 ,已经通过仿真了
Filter source code and test procedures,Finite pulse filter source and test procedures, has been through the simulation (2017-12-27, Verilog, 137KB, 下载5次)
串口通信DHT11，在PC端读取数据,实现传感器的温湿度提取
Communication DHT11 (2017-12-16, Verilog, 1308KB, 下载14次)
简化的16位的cpu的设计，有缓冲器，指令存储器，数据存储器等基本模块组成
The simplified 16 bit CPU design consists of a buffer, instruction memory, data memory and other basic modules (2017-12-01, Verilog, 17833KB, 下载2次)
本代码主要功能是PPM解码，采用Verilog语言，通过移位寄存器和组合电路实现解码。
The main function of this code is PPM decoding. (2017-11-27, Verilog, 168KB, 下载18次)
这是用verilog 实现的同步计数器。
this is a code for synchronous counter written in verilog. (2017-08-12, Verilog, 6KB, 下载4次)