mips处理器
mips processor (2024-03-18, Verilog, 0KB, 下载0次)
FPGA启动器
FPGA Starter (2024-02-22, Verilog, 0KB, 下载0次)
RISCV32处理器
RISCV32 Processor (2023-12-02, Verilog, 0KB, 下载0次)
多核处理器
multicore processor (2023-11-18, Verilog, 0KB, 下载0次)
riscv处理器
riscv cpu (2023-11-11, Verilog, 0KB, 下载0次)
riscv处理器
riscv processor (2023-11-11, Verilog, 0KB, 下载0次)
FPGA收发器，，
FPGA transceiver,, (2023-10-03, Verilog, 0KB, 下载1次)
MIPS处理器，，
MIPS Processor,, (2023-09-07, Verilog, 0KB, 下载0次)
用于Pano G2设备的基于网络的加载器和闪光器
Network based loader and flasher for Pano G2 devices (2022-09-26, Verilog, 9558KB, 下载0次)
FPGA毛刺器基于无齿公司的艺术毛刺器，但适用于破冰船
FPGA glitcher based on toothlessco s arty-glitcher, but for the icebreaker (2019-12-10, Verilog, 26KB, 下载0次)
Open Bench逻辑嗅探器（Devon Core，Verilog）（3.08，带边缘触发器）
Open Bench Logic Sniffer (Demon Core, Verilog) (3.08 with edge triggers) (2017-10-19, Verilog, 90KB, 下载0次)
实现8-3编码器 用简单的Verilog语言实现8-3编码器，可拓展为各种类型编码器
8-3 encoder A simple Verilog language is used to implement 8-3 encoders, which can be expanded to various types of encoders (2020-12-20, Verilog, 56KB, 下载0次)
设计一个挂载在 APB 总线上的计数器，按照 APB 的时序给计数器赋值，主
机通过地址对计数器进行配置，通过数据输入端口给计数器设置计数器最大值，
并通过数据输出端口输出计数器的计数值。该设计还设置了一个计数完成信号，
当计数器满足模式配置后的计数要求时，会将该信号拉高
A counter mounted on the APB bus is designed. The counter is assigned according to the sequence of APB
The computer configures the counter through the address and sets the maximum value of the counter through the data input port,
And output the count value of the counter through the data output port. The design also sets a count completion signal,
When the counter meets the counting requirements after the mode configuration, the signal will be pulled high (2020-06-21, Verilog, 305KB, 下载16次)
使用ise14.7verilog语言编写的四选一数据选择器
4_to_1 data selector (2019-06-09, Verilog, 229KB, 下载0次)
CAN驱动器-MCP2515-接口程序-Verilog
CAN Driver-MCP2515-Interface Program-Verilog (2018-12-09, Verilog, 16KB, 下载11次)
用Verilog实现数码管计数器。
The digital tube counter is realized with Verilog.
The digital tube counter is realized with Verilog. (2018-05-30, Verilog, 1KB, 下载0次)
999计数器，S8置S1递减有复位功能，FPGA验证
999 counter, S8 has S1 reset function, FPGA verification. (2018-05-11, Verilog, 10695KB, 下载0次)
fir滤波器的简单实现，主要用于学习与理解
Simple implementation of the fir filter, mainly for learning and understanding (2018-02-03, Verilog, 1KB, 下载8次)
SDRAM控制器 带仿真模型文件 仿真通过
Simulation model file simulation through SDRAM controller (2017-12-07, Verilog, 2762KB, 下载9次)
DDR2的控制器设计，完成功能的验证，以及仿真测试，
DDR2 controller design, complete function verification, and simulation test, (2017-07-19, Verilog, 22011KB, 下载2次)