综合verilog解析器
synthesized verilog parser (2024-01-24, Verilog, 0KB, 下载0次)
FPGA视频缩放器,,
FPGA videoScaler,, (2023-10-27, Verilog, 0KB, 下载0次)
基于FPGA_CNN_加速器,
FPGA-based_CNN_Accelerator, (2023-10-24, Verilog, 0KB, 下载0次)
在该项目中,8种不同的Verilog HDL D触发器(DFF)实现,包括上升沿触发器和下降沿触发器、同步...,
In this project, 8 distinct Verilog HDL implementations of D flip-flops (DFFs), encompassing rising and falling edge triggers, synchronous and asynchronous resets are designed. (2023-08-09, Verilog, 0KB, 下载0次)
Verilog网络列表分析器,
Verilog netlist parser, (2020-06-13, Verilog, 0KB, 下载0次)
交通灯控制器,,
Traffic_Light_Controller,, (2023-09-05, Verilog, 0KB, 下载0次)
交通灯控制器,,
Traffic_Light_controller,, (2019-07-21, Verilog, 0KB, 下载0次)
交通灯控制器,,
traffic_light_controller,, (2023-08-25, Verilog, 0KB, 下载0次)
交通信号控制器,,
Traffic-Signal-Controller,, (2021-04-23, Verilog, 0KB, 下载0次)
单周期MIPS处理器,,
Single-Cycle-MIPS-Processor,, (2023-08-26, Verilog, 0KB, 下载0次)
多周期MIPS_处理器,,
Multi_Cyclic_MIPS_Processor,, (2023-08-21, Verilog, 0KB, 下载0次)
RISC-V处理器,,
RISC-V-processor,, (2023-08-07, Verilog, 0KB, 下载0次)
便携式RISC-V片上系统实现:RTL、调试器和模拟器
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators (2023-05-28, Verilog, 30715KB, 下载0次)
一个用硬件描述语言verilog实现的同步清零的模55计数器。
A module 55 counter of synchronous zero clearing realized by Verilog. (2020-04-14, Verilog, 576KB, 下载1次)
基于FPGA的温度传感器的读操作Verilog代码
Read operation code of temperature sensor based on FPGA (2018-08-18, Verilog, 11035KB, 下载11次)
利用EDA设计加法器减法器,结合数电知识
Using EDA to design adder subtracting device, combined with digital knowledge. (2018-05-29, Verilog, 23KB, 下载1次)
实现两个数字的比较大小,包括顶层文件和源文件以及测试文件。
To achieve the size of the two figures. (2017-11-12, Verilog, 1KB, 下载1次)
产生8bit随机数,采用线性反馈移位寄存器
The 8bit random number is generated by using linear feedback shift register (2017-11-06, Verilog, 99KB, 下载3次)
用半加器搭建全加器 使用Verilog语言
Using a half adder to build a full adder, using the Verilog language (2017-09-18, Verilog, 274KB, 下载1次)
这个是一个计数器的程序,能够帮助初学者有效的理解计数器
This is a counter program, can help beginners effectively understand the counter (2017-07-11, Verilog, 4KB, 下载1次)