流水线x86处理器
Pipelined x86 Processor (2024-04-08, Verilog, 0KB, 下载0次)
FPGA收发器
FPGA transceiver (2024-03-07, Verilog, 0KB, 下载1次)
acc解码器h264
acc decoder h264 (2024-02-22, Verilog, 0KB, 下载0次)
Risc V处理器
Risc V processor (2024-01-23, Verilog, 0KB, 下载0次)
用于CNC、机器人应用中伺服驱动器的DDA（数字微分分析器）插值算法。，
DDA (Digital Differential Analyzer) interpolation algorithm for servo driver in CNC, robot applications., (2023-10-24, Verilog, 0KB, 下载0次)
微控制器Verilog项目，，
Microcontroller Verilog projects,, (2023-10-19, Verilog, 0KB, 下载0次)
基于RISC-V的5级流水线处理器实现，具有4个流水线寄存器，
RISC-V based 5 stage pipelined processor implementation with 4 pipeline registers, (2023-09-28, Verilog, 0KB, 下载0次)
带简单包装器的加速器RTL设计（使用系统verilog的正弦函数），
Accelerator RTL design with a simple wrapper (sinus function using system verilog), (2021-03-10, Verilog, 0KB, 下载0次)
微控制器_8位，，
micro_controller_8bit,, (2023-08-24, Verilog, 0KB, 下载0次)
我的逻辑分析器。使用FPGA的块RAM进行存储的逻辑分析器。，
My Logic Analyzer. A logic analyzer using an FPGA s block RAMs for storage., (2017-01-12, Verilog, 0KB, 下载0次)
实现1602 LCD、温度传感器和电位计的Verilog PWM风扇控制器
Verilog PWM fan controller implementing a 1602 LCD, a temperature sensor, and a potentiometer (2018-01-04, Verilog, 1014KB, 下载0次)
Verilog课程设计，基于FPGA的出租车计费器
Verilog course design, taxi meter based on FPGA (2021-01-24, Verilog, 369KB, 下载0次)
使用verilog实现的双电梯控制器，1-9层，仿真通过
a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed (2020-06-17, Verilog, 245KB, 下载9次)
滤波器生成，基于vivado ip生成高低通滤波器
Filter generation, generate high and low pass filters based on vivado ip (2020-04-21, Verilog, 17KB, 下载6次)
半带滤波器，用于sigma-delta DAC中的设计
Half-band filter for sigma-delta DAC design (2019-05-08, Verilog, 3KB, 下载11次)
完成verilog hdl比较器设计及验证，通过改程序对软件使用和仿真有初步认识和了解
Complete the comparator design and verification. (2018-11-14, Verilog, 2789KB, 下载0次)
8.22 出租车计价器VHDL程序与仿真具体示例
8.22 Taximeter VHDL program and simulation (2018-08-28, Verilog, 85KB, 下载4次)
等精度频率计，设置不同的闸门，使得测得的结果不随频率的变化而发生精度的变化，测量范围1-25MHZ，在Altera cycloneIII芯片的FPGA开发板上实现。
The same precision frequency meter sets different gates so that the measured results do not change with the change of frequency. The measurement range is 1-25MHZ, and it is realized on the FPGA development board of the Altera cycloneIII chip. (2018-06-06, Verilog, 6970KB, 下载12次)
基于AHB总线的sram控制器，带有memory bist
SRAM controller based on AHB bus (2018-05-19, Verilog, 3178KB, 下载52次)
1. 奇同位產生及檢查器
2. function : 4對一多工器
3. task : 8位元全0全1檢查器
1. Odd parity generation and checker
Function: 4 pairs of a multiplexer
3. task: 8 bit all 0 all 1 checker (2018-01-07, Verilog, 96KB, 下载1次)