高级微控制器和片上系统：Lorenz系统，Mandelbrot集，多处理器鼓，最终项目
Advanced Microcontrollers and System-on-Chip: Lorenz System, Mandelbrot Set, Multiprocessor Drum, Final Project (2024-03-16, Verilog, 0KB, 下载0次)
MIPS_单处理器，
MIPS_Single_Processor, (2023-07-25, Verilog, 0KB, 下载0次)
流水线MIPS处理器，
A pipelined MIPS processor, (2021-05-15, Verilog, 0KB, 下载0次)
MIPS流水线处理器，
MIPS Pipelined Processor, (2018-04-04, Verilog, 0KB, 下载0次)
单周期MIPS处理器，
Single-cycle MIPS Processor, (2013-11-06, Verilog, 0KB, 下载0次)
MIPS 32位处理器，
MIPS 32-bit Processor, (2015-05-05, Verilog, 0KB, 下载0次)
简化的MIPS处理器，
A Simplified MIPS Processor, (2022-05-27, Verilog, 0KB, 下载0次)
MIPS32兼容微处理器。，
A MIPS32 compatible microprocessor., (2015-03-08, Verilog, 0KB, 下载0次)
5级MIPS处理器，
5 Stage MIPS Processor, (2014-07-04, Verilog, 0KB, 下载0次)
Mips 处理器仿真设计,
Mips processor simulation design, (2016-06-22, Verilog, 0KB, 下载0次)
尝试写入sata控制器
try write sata controller (2020-12-30, Verilog, 526KB, 下载0次)
单APB PWM定时器
SINGLE APB PWM TIMER (2020-09-27, Verilog, 0KB, 下载0次)
流水线RISC-V处理器
Pipelined RISC-V Processor (2017-05-05, Verilog, 86KB, 下载0次)
使用Verilog HDL设计了一个模拟的8位单周期处理器，该处理器包括ALU、寄存器堆等...
Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic (2019-01-28, Verilog, 751KB, 下载0次)
Verilog RS232增强同步UART和RS232调试器HDL核心与PC主机RS232实时十六进制编辑器查看器主机实用程序...
Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility. (2022-01-15, Verilog, 590KB, 下载0次)
一些用Modelsim仿真的verilog源代码，包括计数器，移位寄存器等。
Some Verilog source codes simulated by Modelsim include counter, shift register, etc. (2020-04-14, Verilog, 2412KB, 下载1次)
基于FPGA平台的FIR滤波器实现，结合明德杨实验板及设计思路进行验证
Implementation of FIR filter based on FPGA platform (2020-04-09, Verilog, 25KB, 下载1次)
用有限状态机实现的序列检测器的rtl代码和相关的testbench
RTL code of sequence detector implemented by finite state machine and related testbench (2019-12-28, Verilog, 1KB, 下载0次)
本代码为verilog语言编写的按键计数器代码，适用于FPGA小脚丫开发版
Key counter of Beijing University of Posts and Telecommunications (2018-11-30, Verilog, 13KB, 下载3次)
altera 的新器件arria 10高速收发器设计手册
Altera new device, arria 10 high speed transceiver design manual (2017-07-28, Verilog, 4483KB, 下载5次)