这是32位单周期微体系结构MIPS处理器的实现。单个周期在一个周期内执行整个指令。换句话说，指令获取、指令解码、执行、写回和程序计数器更新在单个时钟周期内发生。
This is an implementation of 32-bit single-cycle microarchitecture MIPS processor. The single cycle executes an entire instruction in one cycle. In other words, instruction fetch, instruction decode, execute, write back, and program counter update occurs within a single clock cycle. (2024-07-21, Verilog, 0KB, 下载0次)
该项目是一个PWM信号发生器，它创建了一个正弦波，频率变化在100 Hz和700 Hz之间，步长为100 in 100 Hz，通过UART接口进行操作。
This project is a PWM signal generator that creates a sine wave, with frequency variation between 100 Hz and 700 Hz with steps of 100 in 100 Hz, which is manipulated through a UART interface. (2024-04-23, Verilog, 0KB, 下载0次)
基于iverilog实现rtl和tb文件的自动编译和仿真,并打开gtkwave查看波形
Realize automatic compilation and simulation of rtl and tb files based on iverilog, and open gtkwave to view waveforms (2023-12-09, Verilog, 0KB, 下载0次)
通过FSM机构控制的电梯设计的Verilog设计代码和测试台。覆盖率和波形的报告也包括...，
Verilog design code and testbench for an elevator design controlled thorugh FSM mechanism. Reports of the coverage adn waveforms are also provided along with the code. (2023-10-19, Verilog, 0KB, 下载0次)
上板调试过的spi程序，用singaltap抓取波形，没有问题，可在此基础上修改
SPI program debugged on board, grabbing waveform with singaltap, no problem, can be modified on this basis (2021-04-12, Verilog, 5038KB, 下载0次)
4位乘法器，实现quartusII 编程，包含项目源码以及已经生成的仿真波形
4 bit multiplier, achieve QuartusII programming, including the source code of the project and has generated the simulation waveform (2021-03-27, Verilog, 4181KB, 下载2次)
数字锁相环，输出脉冲波形，与模拟锁相环的区别与联系
Digital PLL, output pulse waveform,Difference and connection between PLL and analog PLL (2020-07-26, Verilog, 462KB, 下载1次)
利用FPGA实现VGA分辨率800*600的显示，通过对clk信号分频得到vga的行场信号，然后逐行将视频显示信号输出。
FPGA is used to realize the display of VGA resolution of 800 * 600. The line field signal of VGA is obtained by dividing CLK signal frequency, and then the video display signal is output line by line. (2020-06-14, Verilog, 1KB, 下载0次)
单周期32位RI型指令CPU，在ISE上进行波形仿真
Single cycle 32-bit RI instruction CPU, waveform simulation on ISE (2020-06-06, Verilog, 7492KB, 下载1次)
单周期32位R型指令CPU，在ISE进行波形仿真
Single cycle 32-bit R-type instruction CPU (2020-06-06, Verilog, 3901KB, 下载0次)
crc编码，在串行通信过程中通过编码减少错误发生
CRC code, in the process of serial communication by coding to reduce the occurrence of errors (2020-05-01, Verilog, 1KB, 下载1次)
双通道AD9226高速采集代码，使用逻辑分析仪观察波形。
Double channel ad9226 high-speed acquisition code, using logic analyzer to observe the waveform. (2019-12-24, Verilog, 10192KB, 下载1次)
通过quartus实现bpsk调制过程，已调整好波形
Through quartus to realize the BPSK modulation process, the waveform has been adjusted (2019-06-05, Verilog, 24266KB, 下载0次)
在数字传输系统中，因为存在噪声，信道衰落等干扰因素，会使传输的信号发生错误，产生误码。虽然数字信号的传输为了防止误码而会进行信道编码，增加传输码的冗余，例如增加监督位等来克服信号在信道传输过程中的错误，但这种检错纠错能力是有限的。例如当出现突发错误，出现大片误码时，这时信道的纠错是无能为力的。而卷积交织器可以将原来的信息码打乱，这时尽管出现大面积突发性错误，这些可以通过解交织器来进行分散，从而将大面积的错误较为平均地分散到不同的码段，利于信道纠错的实现。
In the digital transmission system, because of the existence of noise, channel fading and other interference factors, the transmission signal will be wrong, resulting in error code. Although channel coding and redundancy of transmission codes are increased in order to prevent errors in digital signal transmission, such as increasing supervisory bits, to overcome errors in channel transmission, this error detection and correction capability is limited. For example, when a burst error occurs and a large number of errors occur, the channel error correction is powerless. Convolutional interleaver can scramble the original information code. In spite of large-scale burst errors, these can be dispersed by de-interleaver, so that large-scale errors can be more evenly distributed to different code segments, which is conducive to the realization of channel error correction. (2019-05-14, Verilog, 367KB, 下载4次)
ads830高速AD驱动模块，verilog完整代码，加signaltapII波形仿真，通过串口发送显示
Ads830 high speed AD drive module (2018-07-11, Verilog, 7063KB, 下载5次)
波形数据上升下降沿的检测程序，已经经过仿真验证
The detection program of the rising descending edge of the waveform data has been verified by simulation (2018-03-01, Verilog, 36KB, 下载1次)
依据卫星导航原理，通过Intel接口控制产生37颗北斗卫星对应的PRN（B1I）码。系统时钟10.023MHz
According to the principle of satellite navigation, the PRN (B1I) code corresponding to the 37 Beidou satellites is generated by the control of Intel interface. System clock 10.023MHz (2017-10-11, Verilog, 500KB, 下载2次)
关于vga接口的程序 仿真成功 可供学习使用
VGA interface on the program, simulation success, for learning to use (2017-08-28, Verilog, 5810KB, 下载1次)
SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形
SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform (2017-08-02, Verilog, 4579KB, 下载5次)
能够实现正弦波的输出以及通过频率控制字与相位控制字控制正弦波的相位与频率。
The output of the sine wave can be realized and the phase and frequency of the sine wave can be controlled by two control words. (2017-07-05, Verilog, 3KB, 下载2次)