移位寄存器、多路复用器、触发器、算术逻辑单元、比较器、计数器、有限状态机、，
Shift Register, Multiplexer, Flipflop, Arithmetic Logic Unit, Comparator, Counter, Finite State Machine, (2023-08-01, Verilog, 0KB, 下载0次)
32位Mips处理器，具有ALU、控制器、ALU控制器、指令存储器、数据存储器、多个多路复用器等。，
32 Bit Mips processor featuring an ALU, controller, ALU Controller, instruction memory, data memory, multiple multiplexors, ect., (2021-12-08, Verilog, 0KB, 下载0次)
处理器系统，处理器加上存储器，从存储器取出指令放入处理器执行
processor system, instructions stored in ROM, a counter generate address and the processor execute instructions. (2020-10-10, Verilog, 11101KB, 下载1次)
单周期32位RIJ型指令CPU，在ISE上进行波形仿真，在FPGA上进行实现
Single cycle 32-bit Rij instruction CPU, waveform simulation on ise and Implementation on FPGA (2020-06-06, Verilog, 7721KB, 下载5次)
38译码器，D触发器，全加器，计数器，抢答器，优先编码器，111序列检测器，并行输入转串行输出
poor English.
38 decoder, D trigger, full adder, counter, scrambler, priority encoder, 111 sequence detector, parallel input to serial output (2020-05-18, Verilog, 4235KB, 下载2次)
定时计数器， Verilog语言，FPGA
timer and counter, Verilog language, FPGA (2020-01-22, Verilog, 2KB, 下载3次)
寄存器设计文件，寄存器输入输出以及读写控制，寄存器的配置
Register design and read-write control (2019-11-19, Verilog, 13KB, 下载2次)
实现按键消抖，避免误触发造成不必要的翻转使按键不灵敏、记录按键数量发生错误。并且可更改按键数量。
The key shaking is realized to avoid unnecessary flipping caused by wrong triggering, which makes the keys insensitive and records the number of keys wrong. And you can change the number of keys. (2019-05-30, Verilog, 5455KB, 下载0次)
数字电路加法器、译码器、比较器...verilog实现
adder,decoder,comparer... in verilog (2019-02-18, Verilog, 11KB, 下载0次)
verilog编码器、计数器、加法器的程序
Verilog encoder, counter, adder procedures (2019-01-26, Verilog, 9528KB, 下载3次)
基于Avalon总线的脉冲计数模块，脉冲采样频率和中断周期可配置，用于外部脉冲多通道计数，文件中包含仿真文件，已通过信号发生器验证脉冲计数精度，也可通过本人上传的另外一个脉冲产品模块avalon_slave_plusgenerator搭配使用，验证其采样精度。
The pulse counting module based on Avalon bus can be configured for external pulse multi-channel counting. The file contains simulation files. The pulse counting accuracy has been verified by signal generator. The sampling accuracy can also be verified by another pulse genertor module avalon_slave_plusgenerator uploaded by me. (2018-08-14, Verilog, 3KB, 下载5次)
RS(204,188)译码器说明
原文件：
rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）,
Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。
ROM及初始化文件：
rom_inv.v（求逆运算）, rom_power.v（求幂运算）；
rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。
仿真波形：
rs_decoder.vwf。
RS (204188) decoder explanation
Original document:
Rs_decoder.v (top level file), SyndromeCalc.v (Computational adjoint), BM_KES.v (BM solving key equations).
Forney.v (Forney algorithm for error sample), CheinSearch.v (search wrong location), ff_mul.v (finite field multiplication).
ROM and initialization files:
Rom_inv.v (inverse operation), rom_power.v (exponentiation operation).
Rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization file).
Simulation waveform:
Rs_decoder.vwf. (2018-07-14, Verilog, 15KB, 下载7次)
基于basys3的计时器，编译环境为vivado.
The timer is based on basys3, and the compiler environment is vivado. (2018-06-05, Verilog, 842KB, 下载4次)
基于FPGA的高阶FIR滤波器实现，Verilog语言
Implementation of high order FIR filter based on FPGA,
Verilog language (2018-05-29, Verilog, 2606KB, 下载34次)
38译码器原理图，仿真图文件，可直接在Quartus II中打开查看。
38 decoders' schematic files, which can be compiled and simulated directly. (2018-05-24, Verilog, 1432KB, 下载2次)
基于FPGA的PWM波生成程序，用于控制步进电机。
A PWM wave generater for driving stepper motor. (2018-05-07, Verilog, 18766KB, 下载22次)
SRAM读写测试实例，每秒钟进行一次单字节的SRAM
读和写操作，用chipscope查看时序波形。
SRAM read and write test instances, each time a single byte SRAM
Read and write operations, use chipscope to see the timing waveform. (2017-09-06, Verilog, 1309KB, 下载3次)
本设计为六位约翰逊(Johnson)计数器，首先给大家介绍一下什么是约翰逊计数器，它又称扭环计数器,是一种用n位触发器来表示2n个状态的计数器。它与环形计数器不同,后者用n位触发器仅可表示n个状态。2~n进制计数器(n为触发器的个数)有2~n个状态。若以6位二进制计数器为例,它可表示64个状态。但由于8421码每组代码之间可能有二位或二位以上的二进制代码发生改变,这在计数器中特别是异步计数器中就有可能产生错误的译码信号,从而造成永久性的错误。而约翰逊计数器的状态表中,相邻两组代码只可能有一位二进制代码不同,故在计数过程中不会产生错误的译码信号。鉴于上述优点,约翰逊计数器在同步计数器中应用比较广泛。
This design is a six-bit Johnson counter, first of all to introduce what is the Johnson counter, it also called the torsion ring counter, is a kind of n-bit trigger to represent the 2n state of the counter. It differs from a ring counter, which uses n-bit triggers only to represent N states. The 2~n feed counter (n is the number of triggers) has a 2~n state. For example, a 6-bit binary counter can represent 64 states. However, because there may be two-bit or more than two bits of binary code between each set of code in 8421 yards, it is possible to produce the wrong decoding signal in the counter, especially in the asynchronous counter, resulting in a permanent error. In the state table of the Johnson counter, the adjacent two groups of code may only have one binary code, so there will be no wrong decoding signal in the counting process. In view of the above advantages, Johnson counter is widely used in synchronization counter. (2017-08-31, Verilog, 6KB, 下载9次)
APB 总线。可以实现单个数据在总机与从机之间的读写功能
This can achieve the read and write functions of a single data between the master and the slave . (2017-08-22, Verilog, 1KB, 下载25次)
积分器的一种实现方法：每级积分器都是一个反馈系数为1的单极点IIR滤波器, 其传递函数为:
An implementation of an integrator: each stage integrator is a single pole IIR filter with a feedback factor of 1: (2017-07-08, Verilog, 136KB, 下载9次)