实现数字频率合成实验，加载数据ram,形成波形
The experiment of digital frequency synthesis is realized, and the data RAM is loaded to form the waveform (2020-11-10, Verilog, 26282KB, 下载2次)
dds 直接频率生成 工程 代码 源文件
DDS direct frequency generation of engineering code source file (2020-09-16, Verilog, 11143KB, 下载1次)
基于fpga的信号发生器，通过调整按键可以生成正弦波，方波，三角波，锯齿波
Sine wave, square wave, triangular wave, sawtooth wave (2020-07-19, Verilog, 15940KB, 下载4次)
改变频率字，实现任意频率（0.00016hz~6Mhz）sine波形输出。
Change the frequency word to realize arbitrary frequency(0.00016hz~6Mhz)sine waveform output. (2020-06-24, Verilog, 3231KB, 下载0次)
读取单片机写入的控制字，将其写入DDS的寄存器
Read the control word written by MCU and write it into the register of DDS (2020-04-26, Verilog, 6KB, 下载4次)
生成指定的信号，用来数据输入，这里生成了三种波形，非常牛比，
Generate the specified signal for data input. Here, three waveforms are generated, which are very Niubi, (2020-03-31, Verilog, 30KB, 下载0次)
直接数字合成（Direct Digital Synthesizer，简称DDS）是一种数字电子方式，它从一个单一（或混合）的频率源中产生任意波形和频率
Direct digital synthesizer (DDS) is a kind of digital electronic mode, which produces arbitrary waveform and frequency from a single (or mixed) frequency source (2020-03-30, Verilog, 23651KB, 下载0次)
FPGA做波形发生器，产生8种波形，包括三角波，正弦波，锯齿波，方波等。
FPGA is used as waveform generator,Generate 8 waveforms, including triangle, sine, sawtooth, square, etc. (2019-07-16, Verilog, 2035KB, 下载4次)
verilog生成DDS,并且具有调幅度的功能，需要有DAT文件。
Verilog generates DDS, and has the function of amplitude modulation. It needs DAT files. (2018-10-14, Verilog, 13266KB, 下载0次)
DDS生成正弦波和方波，其中正弦波调用rom的ip核进行查表产生波形，方波直接用计数器counter生成。时钟通过PLL ip核进行分频。使用中注意我的是quartus15.1，别的版本打开文件可能要重建IP核，其中ROM对应的.v文件中的数据文件的绝对地址要改，改成你的就行。
DDS generates sine wave and Fang Bo, where the sine wave calls the IP core of ROM to look up the table to generate waveform, and the square wave is generated directly by counter counter. The clock is divided by the PLL IP core. In the use of my attention is quartus15.1, other versions of the open file may be to rebuild the IP core, of which the ROM corresponding to the.V file of the absolute address of the data file to change to your right. (2018-06-14, Verilog, 8456KB, 下载3次)
用verilog编写的dds程序，包含顶层和各模块
DDS program written in Verilog (2018-05-29, Verilog, 51KB, 下载2次)
使用verilog语言实现包括正弦波、余弦波、锯齿波的发生。
Verilog realization of waveform generator (2018-04-30, Verilog, 1KB, 下载3次)
dds算法，调用xilinx IP ，ise
DDS algorithm, call Xilinx IP, ISE (2018-04-17, Verilog, 5594KB, 下载8次)
DDS FPGA Verilog vhdl
DDS FPGA Verilog vhdl (2018-04-15, Verilog, 176KB, 下载16次)
该文件是dds工程，用的是单片机和FPGA开发板组合实现对存储在FPGA中rom里面的波形数据的，调频率（调频范围是1-1MHz），波形在示波器上显示，单片机实现控制字的发送及控制频率，FPGA实现控制字的接收和存储波形数据,输出波形
The file is a DDS project. It is a combination of single chip microcomputer and FPGA development board to realize the amplitude modulation of the waveform data stored in the ROM in FPGA. The frequency modulation rate, the waveform shows on the oscilloscope, the MCU realizes the transmission of the control word, and the FPGA realizes the receiving and storing the waveform data of the control word. (2018-04-13, Verilog, 1039KB, 下载2次)
基于查找表的DDS的Verilog实现，分为相位累加器模块、ROM模块和顶层DDS模块
Verilog implementation of DDS based on lookup table (2018-04-03, Verilog, 3KB, 下载8次)
实现了DDS的verilog源代码，可以使用
ajhsjdhjkshfjhfsjkjksa (2018-02-27, Verilog, 3KB, 下载3次)
dds输出一个正弦波，通过修改频率控制字来控制频率
DDS outputs a sine wave to control frequency by modifying the frequency control word (2017-11-27, Verilog, 5437KB, 下载7次)
可以实现DDS 的正负线性扫频以及在线参数设置
DDS ad9914/ad9915 code (2017-10-23, Verilog, 5KB, 下载30次)
基于FPGA的DDS正弦信号设计，文件中有源代码
Design of DDS based on FPGA (2017-08-06, Verilog, 50KB, 下载11次)