响尾蛇模拟帧数据发生器，
Sidewinder simulated frame data generator, (2023-10-24, Verilog, 0KB, 下载0次)
PWM发生器的Verilog代码
Verilog code for PWM Generator (2018-03-07, Verilog, 782KB, 下载0次)
FPGA PWM发生器和电机控制器模块
FPGA PWM generator and motor controller modules (2021-03-09, Verilog, 5KB, 下载1次)
DDS频率控制寄存器可以串行或并行加载和存储用户输入的频率控制码...
The DDS frequency control register can load and store the user-entered frequency control code serially or in parallel, while the phase accumulator adds phases to each clock cycle according to the frequency control code to obtain a phase value, and the sine calculator calculates the digitized sine wave amplitude for that phase value (2021-11-15, Verilog, 17KB, 下载0次)
基于FPGA的信号发生器
FPGA based signal generator (2015-06-25, Verilog, 8321KB, 下载0次)
高斯噪声发生器Verilog IP核
Gaussian noise generator Verilog IP core (2023-05-22, Verilog, 10986KB, 下载0次)
简易信号发生器，可以实现简单的信号实现，任意波编辑，通过FPGA的verilog语言实现功能，自测可以正常使用。
Simple signal generator, can realize simple signal realization, arbitrary wave editing, through FPGA Verilog language function, self-test can be used normally. (2021-03-25, Verilog, 2110KB, 下载1次)
一个很简单的 verilog 写的 时钟 发生器，产生1us，10us，1ms ，100ms 等cllk
a simple verilog module , the module generate clk ,such as 1us 10us 1ms 10ms 100ms (2021-03-17, Verilog, 1KB, 下载0次)
pfm驱动方波发生器,使用FPGA驱动2路igbt
PFM is used to drive square wave generator and FPGA is used to drive 2-way IGBT (2021-02-17, Verilog, 3KB, 下载2次)
1，使用quartus,生成.mif文件，然后导入正弦波数据
2.利用LPM功能定制一个8bit数据宽度，128字节深度的ROM;利用MATLAB和FPGA实现基于ROM的正弦波发生器.
1. Use quartus to generate. MIF file, and then import sine wave data
2. Use LPM function to customize a ROM with 8 bit data width and 128 byte depth; use MATLAB and FPGA to realize the sine wave generator based on ROM (2020-09-16, Verilog, 2343KB, 下载2次)
打包好的ISE工程，可以直接使用，通过ISE内部调用的IP核产生输出正弦信号。
The packaged ISE project, which can be used directly, generates output sinusoidal signals through the IP core invoked internally by ISE. (2020-07-31, Verilog, 13009KB, 下载2次)
HDMI 彩条发生器，1080i,1080p
HDMI color bar generator (2020-01-25, Verilog, 3KB, 下载1次)
pwn信号发生器的源代码和仿真图，该程序可实现频率可调，占空比可调的pwm信号
Pulse generator with adjustable duty cycle (2019-12-12, Verilog, 27KB, 下载2次)
设计m序列发生器,其特征方程为 ，输出数字序列信号m_sequence码速率为10Mbps
Design of m-Sequence Generator (2019-03-17, Verilog, 31KB, 下载5次)
数字示波器实验，利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。
In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA. (2019-03-13, Verilog, 3791KB, 下载6次)
基于FPGA的两路的频率可调的正弦信号发生器，verilog语言
Two way frequency adjustable sinusoidal signal generator based on FPGA, Verilog language (2018-11-17, Verilog, 11378KB, 下载2次)
system generatpr 的工程，实现用dds模块产生sine和cosine两路信号
The Engineering of system generator, using dds Module to generate sine and cosine signals (2018-09-10, Verilog, 27KB, 下载0次)
二选一多路选择器，含程序代码，含仿真波形图
Two select a multi path selector, including program code, including simulation waveform. (2018-05-17, Verilog, 109KB, 下载1次)
自己写的FIR八戒低通滤波器，仅供参考
Write your own FIR eight quit low-pass filter, for reference only (2017-07-28, Verilog, 6732KB, 下载6次)
使用FPGA控制VGA显示波形，显示汉字，水平垂直可调
FPGA controls the VGA display waveform (2017-07-23, Verilog, 3KB, 下载6次)