Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation. (2024-05-26, Verilog, 0KB, 下载1次)
http://www.pudn.com/Download/item/id/1716720994510511.html
与飞利浦SAA1099 6语音可编程声音发生器（PSG）芯片一起提交的TinyTapeout。
TinyTapeout submission with the SAA1099 a 6-voice programmable sound generator (PSG) chip from Philips. (2023-11-16, Verilog, 0KB, 下载0次)
包括开发的HDL代码、波形图和ARM处理器实现的示意图。代码是根据......制定的...，
Includes developed HDL codes, pictures of waveforms and schematics for the implementation of an ARM processor. Codes were/are developed by moein maleki and ashkan jafari, for Architecture Lab, Fall of 2022. (2023-09-23, Verilog, 0KB, 下载0次)
在该呼吸罩加减器部分中，包含测试台和模拟波形，
in this respiratory cover adder and subtractor part and containing testbench and simulation waveform, (2020-12-21, Verilog, 0KB, 下载0次)
字符波形生成器,生成特定字符的字模,以供在Verilog端口产生对应字符样式的时序激励。,
Character waveform generator, which generates the font of a specific character for generating timing excitation of corresponding character style on Verilog port., (2019-02-06, Verilog, 0KB, 下载0次)
使用eSim、使用ngveri（Makerchip）和ngspice的3位数字控制PWM发生器
3bit digitally controlled PWM Generator using eSim, using ngveri(Makerchip) and ngspice (2022-06-18, Verilog, 5320KB, 下载0次)
该存储库包含使用eSim的8位数字正弦波发生器的混合信号设计的尝试
This repository contains an attempt to mixed signal design of a 8-bit Digital Sine wave generator using eSim (2022-03-12, Verilog, 6534KB, 下载0次)
从涉及FPGA的架构中创建模拟正弦信号的项目。它是用一个DDS核心来生成...
Project which creates an analogic sine signal from an architecture that involves FPGA. It were used a DDS core to generate the sine and SPI communication to control DAC conversor (AD5791 Analog Devices). To choose the sine frequency and the update frequency of a new data we developed a cpp application. The "documentation" folder has more (2014-03-26, Verilog, 6581KB, 下载0次)
以FPGA为目标，用VHDL语言编写了一个具有环形振荡器结构的真随机数发生器。
A true random number generator with ring oscillators structure written in VHDL targeting FPGA s. (2020-09-22, Verilog, 12KB, 下载0次)
异步FIFO的Verilog实现，已经建立好仿真平台，使用modelsim仿真可以直接查看仿真波形 (2022-06-02, Verilog, 546KB, 下载0次)
http://www.pudn.com/Download/item/id/1654135500535258.html
示波器设计，首先，AD模块对模拟信号进行采样，触发电路根据采样信号判断触发条件。满足触发条件后，连续采样一定数量的点（本系统中为640个点），存储到RAM中。峰峰值、频率计算模块对RAM中储存的波形数据进行计算，得到波形的频率以及峰峰值；VGA模块将波形显示出来，并显示计算得到的峰峰值和频率数值。
Firstly, the ad module samples the analog signal, and the trigger circuit judges the trigger condition according to the sampling signal. After meeting the trigger conditions, a certain number of points (640 points in this system) are sampled continuously and stored in RAM. The peak to peak and frequency calculation module calculates the waveform data stored in RAM to obtain the frequency and peak to peak of the waveform; the VGA module displays the waveform and displays the calculated peak to peak and frequency values. (2021-01-02, Verilog, 230KB, 下载1次)
可用FPGA实现DA输出，输出波形有三角波和正弦波形
The Da output can be realized by FPGA, and the output waveform includes triangle wave and sine wave (2020-06-27, Verilog, 178KB, 下载4次)
在quartus上运行16QAM仿真，实现在modelsim上的波形仿真
Running 16QAM simulation on quartus (2020-04-27, Verilog, 9360KB, 下载2次)
非常详细的串行输入代码，内有仿真的波形图，还有编写代码的状态图和思路讲解。
very detailed explanation (2020-03-04, Verilog, 87KB, 下载2次)
压缩包中包含一些基本的eda设计文件,如正弦波发生器，vga显示图像
The compression package contains some basic EDA design files, such as sine wave generator, VGA display image (2019-04-25, Verilog, 14932KB, 下载0次)
周期为15的M序列发生器，用quartus仿真成功。
M sequence generator with a period of 15 (2018-05-11, Verilog, 8KB, 下载3次)
使用verilog实现两方波之间的移相，已经过验证可行。
Using Verilog to realize the phase shift between two square waves (2018-04-30, Verilog, 1KB, 下载11次)
使用verilog语言实现锯齿波的产生，完美调试成功
The use of Verilog language to produce sawtooth waves (2018-04-30, Verilog, 8KB, 下载4次)
附有m码产生verilog文件和测试文件，以及详细说明。读者可根据说明配置任意级m序列发生器
With M code, Verilog files and test files are produced and detailed. The reader can configure an arbitrary m sequence generator according to the instructions (2018-01-04, Verilog, 72KB, 下载9次)
RS（罗德施瓦茨）信号源，内部ARM波形文件，输出4倍采样率噪声信号。
AWGN模型。
A wave data file outputing a AWGN signal based on RS signal generator. (2017-07-06, Verilog, 497KB, 下载1次)