This project focuses on the implementation of Direct Digital Synthesis (DDS) to generate sine waves using the lookup table (LUT) method, coupled with an 8-bit Digital-to-Analog Converter (DAC). (2024-05-24, Verilog, 0KB, 下载0次)
http://www.pudn.com/Download/item/id/1716520988265134.html
本课题对设计的变占空比脉宽调制波发生器进行了仿真。我们可以产生PWM波并改变其...，
This project simulates the designed Pulse Width Modulated Wave Generator with Variable Duty Cycle. We can generate PWM wave and varry its DUTYCYCLE in steps of 10% (2023-10-26, Verilog, 0KB, 下载0次)
使用通用仪器的AY-3-8913 3语音可编程声音发生器（PSG）芯片提交TinyTapeout，
TinyTapeout submission with the AY-3-8913 a 3-voice programmable sound generator (PSG) chip from General Instruments, (2023-10-03, Verilog, 0KB, 下载0次)
该项目实现了一个32组32位寄存器堆的纯软件实现,并可以通过GTKWave查看仿真波形,
This project has realized a pure software implementation of a 32 group 32-bit register stack, and can view the simulation waveform through GTKWave, (2020-01-31, Verilog, 0KB, 下载0次)
与课程CO204-数字系统设计软件实验室相关的电路代码和模拟，
Codes and simulation of circuits pertaining to software Lab for Course CO204 - Design of Digital Systems, (2017-11-09, Verilog, 0KB, 下载0次)
FPGA Messbauer硬件（发生器，伽马源信号的模拟，注册和放大
FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified (2019-08-26, Verilog, 0KB, 下载0次)
数字锁相环，输出脉冲波形，与模拟锁相环的区别与联系
Digital PLL, output pulse waveform,Difference and connection between PLL and analog PLL (2020-07-26, Verilog, 462KB, 下载1次)
单周期32位R型指令CPU，在ISE进行波形仿真
Single cycle 32-bit R-type instruction CPU (2020-06-06, Verilog, 3901KB, 下载0次)
控制8通道dac，ad5308的spi通信，和波形控制
Control 8-channel DAC, ad5308 (2020-05-22, Verilog, 7628KB, 下载5次)
基于CycloneV FPGA与电阻网络的数模转换器代码，能够实现键控更改频率，通过ROM IP核存储波形数据。
Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core. (2020-03-29, Verilog, 11045KB, 下载2次)
实现cpu的构成与仿真测试，可以较为完整的展现测试波形
Realization of CPU composition and simulation test (2019-06-26, Verilog, 166KB, 下载1次)
这是一个调试好的AD9858的verilog配置代码对初学者很有帮助
This is a debugged Verilog code for AD9858, which is very helpful for beginners. (2018-11-16, Verilog, 28KB, 下载9次)
锁相环例程，锁相环测试相关，输出四个不同频率的波形
Phase-locked loop routine (2018-05-11, Verilog, 6029KB, 下载2次)
基于verilog编写的MSK调制程序，modsim仿真波形正确
Verilog based MSK modulation program written, modsim simulation waveform correct (2018-04-26, Verilog, 1059KB, 下载26次)
在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。
In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared. (2018-02-09, Verilog, 47016KB, 下载18次)
依据卫星导航原理，通过Intel接口控制产生37颗北斗卫星对应的PRN（B1I）码。系统时钟10.023MHz
According to the principle of satellite navigation, the PRN (B1I) code corresponding to the 37 Beidou satellites is generated by the control of Intel interface. System clock 10.023MHz (2017-10-11, Verilog, 500KB, 下载2次)
介绍了一种利用FPGA硬件平台生成高斯随机数的算法
An algorithm for generating Gauss random numbers using FPGA hardware platform is introduced. (2017-10-11, Verilog, 32KB, 下载4次)
介绍了一种利用FPGA硬件平台生成高斯随机数的算法。
An algorithm for generating Gauss random numbers using FPGA hardware platform is introduced (2017-10-11, Verilog, 3245KB, 下载4次)
关于vga接口的程序 仿真成功 可供学习使用
VGA interface on the program, simulation success, for learning to use (2017-08-28, Verilog, 5810KB, 下载1次)
多周期CPU的verilog代码，用vivado可以仿真出波形
multi-cycle CPU by verilog and using vivado to simulate. (2017-07-12, Verilog, 5738KB, 下载1次)