基于iverilog实现rtl和tb文件的自动编译和仿真,并打开gtkwave查看波形
Realize automatic compilation and simulation of rtl and tb files based on iverilog, and open gtkwave to view waveforms (2023-12-09, Verilog, 0KB, 下载0次)
通过FSM机构控制的电梯设计的Verilog设计代码和测试台。覆盖率和波形的报告也包括...，
Verilog design code and testbench for an elevator design controlled thorugh FSM mechanism. Reports of the coverage adn waveforms are also provided along with the code. (2023-10-19, Verilog, 0KB, 下载0次)
上板调试过的spi程序，用singaltap抓取波形，没有问题，可在此基础上修改
SPI program debugged on board, grabbing waveform with singaltap, no problem, can be modified on this basis (2021-04-12, Verilog, 5038KB, 下载0次)
4位乘法器，实现quartusII 编程，包含项目源码以及已经生成的仿真波形
4 bit multiplier, achieve QuartusII programming, including the source code of the project and has generated the simulation waveform (2021-03-27, Verilog, 4181KB, 下载2次)
一个编码解码系统，其中包含一个信号发生器（用查找表方式实现）、一个m序列生成器（用来编码和解码用）、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。
An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data. (2021-03-15, Verilog, 328KB, 下载2次)
ADC9650测试程序，对ad9914生成波形进行ADC采样，可以在VIVADO2017.4上直接运行，已验证.
Adc9650 test program, ad9914 waveform generated by ADC sampling, can be run directly on vivado 2017.4, has been verified (2020-08-07, Verilog, 50851KB, 下载38次)
利用FPGA实现VGA分辨率800*600的显示，通过对clk信号分频得到vga的行场信号，然后逐行将视频显示信号输出。
FPGA is used to realize the display of VGA resolution of 800 * 600. The line field signal of VGA is obtained by dividing CLK signal frequency, and then the video display signal is output line by line. (2020-06-14, Verilog, 1KB, 下载0次)
单周期32位RI型指令CPU，在ISE上进行波形仿真
Single cycle 32-bit RI instruction CPU, waveform simulation on ISE (2020-06-06, Verilog, 7492KB, 下载1次)
crc编码，在串行通信过程中通过编码减少错误发生
CRC code, in the process of serial communication by coding to reduce the occurrence of errors (2020-05-01, Verilog, 1KB, 下载1次)
双通道AD9226高速采集代码，使用逻辑分析仪观察波形。
Double channel ad9226 high-speed acquisition code, using logic analyzer to observe the waveform. (2019-12-24, Verilog, 10192KB, 下载1次)
FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源
Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA. (2019-07-29, Verilog, 3119KB, 下载1次)
通过quartus实现bpsk调制过程，已调整好波形
Through quartus to realize the BPSK modulation process, the waveform has been adjusted (2019-06-05, Verilog, 24266KB, 下载0次)
在数字传输系统中，因为存在噪声，信道衰落等干扰因素，会使传输的信号发生错误，产生误码。虽然数字信号的传输为了防止误码而会进行信道编码，增加传输码的冗余，例如增加监督位等来克服信号在信道传输过程中的错误，但这种检错纠错能力是有限的。例如当出现突发错误，出现大片误码时，这时信道的纠错是无能为力的。而卷积交织器可以将原来的信息码打乱，这时尽管出现大面积突发性错误，这些可以通过解交织器来进行分散，从而将大面积的错误较为平均地分散到不同的码段，利于信道纠错的实现。
In the digital transmission system, because of the existence of noise, channel fading and other interference factors, the transmission signal will be wrong, resulting in error code. Although channel coding and redundancy of transmission codes are increased in order to prevent errors in digital signal transmission, such as increasing supervisory bits, to overcome errors in channel transmission, this error detection and correction capability is limited. For example, when a burst error occurs and a large number of errors occur, the channel error correction is powerless. Convolutional interleaver can scramble the original information code. In spite of large-scale burst errors, these can be dispersed by de-interleaver, so that large-scale errors can be more evenly distributed to different code segments, which is conducive to the realization of channel error correction. (2019-05-14, Verilog, 367KB, 下载4次)
实现SRAM的读写，每秒钟进行一次单字节的SRAM读和写操作，用chipscope查看时序波形
Implementation reading and writing of SRAM,SRAM reads and writes single word segments once per second, and USES chipscope to view time series waveforms (2018-08-04, Verilog, 6085KB, 下载0次)
ads830高速AD驱动模块，verilog完整代码，加signaltapII波形仿真，通过串口发送显示
Ads830 high speed AD drive module (2018-07-11, Verilog, 7063KB, 下载5次)
本文件用于测波形频率的verilog代码，是典型的数字频率计的源代码
This document is used to measure the frequency of the Verilog code, the source code of a typical digital frequency meter (2018-04-09, Verilog, 11KB, 下载4次)
波形数据上升下降沿的检测程序，已经经过仿真验证
The detection program of the rising descending edge of the waveform data has been verified by simulation (2018-03-01, Verilog, 36KB, 下载1次)
基于vivado Verilog的伪随机数发生器，采用LFSR算法，并对其进行了升级，使用反馈级联的思想，从最大周期为2^n提升为原来的3-5倍
Based on vivado Verilog pseudo random number generator, using LFSR algorithm, and upgrade it, using the idea of feedback cascade, from the maximum cycle of 2^n to 3-5 times the original (2017-11-06, Verilog, 1845KB, 下载10次)
SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形
SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform (2017-08-02, Verilog, 4579KB, 下载5次)
能够实现正弦波的输出以及通过频率控制字与相位控制字控制正弦波的相位与频率。
The output of the sine wave can be realized and the phase and frequency of the sine wave can be controlled by two control words. (2017-07-05, Verilog, 3KB, 下载2次)