FPGA电机控制器
FPGA Motor Controller (2024-03-31, SystemVerilog, 0KB, 下载0次)
AHB3 Lite SDRAM控制器
AHB3 Lite SDRAM Controller (2024-02-07, SystemVerilog, 0KB, 下载0次)
交通灯控制器
Traffic Light Controller (2024-01-24, SystemVerilog, 0KB, 下载0次)
fpga vga显示器
fpga vga display (2023-12-30, SystemVerilog, 0KB, 下载0次)
fpga光传感器
fpga light sensor (2023-12-30, SystemVerilog, 0KB, 下载0次)
微型RISC-V RV64G处理器
tiny RISC-V RV64G processor (2023-11-19, SystemVerilog, 0KB, 下载0次)
路由器UVM测试台
Router UVM Testbench (2023-10-29, SystemVerilog, 0KB, 下载0次)
经典SV存储器测试台，用于对具有读写操作的存储器模块进行鲁棒验证。，
Classical SV memory testbench for robust validation of memory modules with read and write operations., (2023-10-25, SystemVerilog, 0KB, 下载0次)
基于APB4的PWM控制器，
An APB4-based PWM Controller, (2023-10-15, SystemVerilog, 0KB, 下载0次)
SystemVerilog中的玩具处理器，
Toy processor in SystemVerilog, (2023-10-14, SystemVerilog, 0KB, 下载0次)
RTOS内核接口生成器，
Kernel Interface Generator for RTOS, (2023-09-27, SystemVerilog, 0KB, 下载0次)
双核处理器设计，
Dual Core Processor design, (2018-10-25, SystemVerilog, 0KB, 下载0次)
交通灯控制器，，
Traffic light controller,, (2023-09-09, SystemVerilog, 0KB, 下载0次)
UVM测试台的基本示例，具有简单的序列、驱动程序、监视器、检查器和测试。，
A basic example of a UVM testbench with a simple sequences, driver, monitor, checker, and test., (2019-04-19, SystemVerilog, 0KB, 下载0次)
TinyVers异构SoC由可重构FlexML加速器、RISC-V处理器、eMRAM和电源组成...
TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system. (2023-04-28, SystemVerilog, 13526KB, 下载0次)
DUTH RISC-V微处理器
DUTH RISC-V Microprocessor (2021-03-10, SystemVerilog, 326KB, 下载0次)
朴素教育RISC V处理器
Naive Educational RISC V processor (2023-04-26, SystemVerilog, 97KB, 下载0次)
一种用于FPGA设计的模拟存储器控制器，用于对真实系统性能进行建模
A simulated memory controller for use in FPGA designs that want to model real system performance (2021-04-19, SystemVerilog, 133KB, 下载0次)
VGA控制器生成VGA监视器使用的定时信号，还输出下一个像素地址
VGA Controller generates timing signals used by a vga monitor, outputs also the next pixel address (2019-07-09, SystemVerilog, 3KB, 下载0次)
浮点协处理器（Verilog）
Floating Point Co-Processor (Verilog) (2015-07-08, SystemVerilog, 1940KB, 下载0次)