正弦发生器Verilog
Sine Generator Verilog (2024-03-14, SystemVerilog, 0KB, 下载0次)
uvm框架发生器
uvm framework generator (2023-12-16, SystemVerilog, 0KB, 下载0次)
FPGA波形发生器描述软件
Wave generator description software for FPGA (2023-11-14, SystemVerilog, 0KB, 下载0次)
基本Verilog代码，如Gates、加法器、Subractor、多路复用器、解复用器、触发器等。。。，，
Basic Verilog codes like Gates, adders, subractors, mux, demux, flipflops etc...,, (2023-10-06, SystemVerilog, 0KB, 下载0次)
uvm测试台发生器，
uvm testbench generator, (2021-05-06, SystemVerilog, 0KB, 下载0次)
伪随机序列发生器，，
pseudo random sequence generator,, (2020-08-22, SystemVerilog, 0KB, 下载0次)
为ALU构建SystemVerilog环境，使用OOP测试台组件作为；刺激发生器，驱动器，监视器，记分板。ALU是...，
Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was verified using QuestaSim. (2023-03-04, SystemVerilog, 0KB, 下载0次)
存储器，，
Memory,, (2020-03-14, SystemVerilog, 0KB, 下载0次)
基于FPGA的视觉transformer加速器（哈佛CS205），
FPGA based Vision Transformer accelerator (Harvard CS205), (2023-06-08, SystemVerilog, 0KB, 下载0次)
RISC-V管道处理器，带危险检测单元和转发单元。仅在c...中发生2个时钟的管道暂停...
RISC-V pipeline processor with Hazard Detection Unit and Forwarding Unit. Pipeline stall for 2 clocks occur only in case of RAW dependency. (2020-08-12, SystemVerilog, 20KB, 下载0次)
基于简单SoC的围绕火箭芯片的RISC-V发生器
Simple SoC based around the rocket-chip RISC-V generator (2018-11-01, SystemVerilog, 95KB, 下载0次)
参数化耗电设备和噪声发生器设计
Parameterizable power consumer and noise generator design (2017-04-27, SystemVerilog, 78KB, 下载0次)
HCSR04超声波传感器AXI IP+驱动器
HCSR04 Ultrasonic Sensor AXI IP + Drivers (2022-02-19, SystemVerilog, 3KB, 下载0次)
使用verilog系统verilog仿真结果（vcd波形）显示一些图像。图像将被聚类（使用co...
using verilog/systemverilog simulation result(a vcd wave) to display some image. the image will be clustered(using color quant) to no more than 4 color(wave only support 0/1/x/z) (2019-08-25, SystemVerilog, 139KB, 下载0次)
利用FPGA板和System Verilog设计控制器、DMA、流水线SIMD处理器和GEMM加速器
Utilized FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator (2023-01-18, SystemVerilog, 42322KB, 下载0次)
DAC波形移动块Verilog，，
DAC-Waveform-Moving-Block-Verilog,, (2021-03-09, SystemVerilog, 1461KB, 下载0次)
MIPS处理器，带高速缓存、多循环存储器和浮点协处理器
MIPS processor with cache and multicycle memory and floating-point coprocessor (2022-11-03, SystemVerilog, 1192KB, 下载0次)
YM2149 AY-3-8910系统Verilog和Verilog中的可编程声音发生器。提供双PSG，可编程立体声m...
YM2149 / AY-3-8910 Programmable Sound Generator in SystemVerilog and Verilog. Offers dual PSGs, programmable stereo mixer with bass and treble controls, standard I2S 44.1KHz or 48KHz 16-bit digital audio out, and built-in floating point system clock divider/generator. (2022-09-08, SystemVerilog, 166KB, 下载0次)
简单的UART发射器和接收器
Simple UART transmitter and receiver (2019-06-11, SystemVerilog, 10KB, 下载0次)
《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulat...
The source code of "FPGA Application Development and Simulation" (ISBN: 9787111582786, 2018, 1st edition, China Machine Press). Source Code of the book FPGA Application Development and Simulate (2022-07-10, SystemVerilog, 13274KB, 下载0次)