vhdl数字钟，有校时校分整点报时的基本功能
vhdl digital clock school, the school divided the whole point timekeeping function (2012-09-19, VHDL, 256KB, 下载30次)
数字钟设计 计时计数器用24进制计时电路；
可手动校时，能分别进行时、分的校正；
整点报时；
选做：可设置闹时功能，当计时计到预定时间时，扬声器发出闹铃信号，闹铃时间为4s，并可提前终止闹铃。
Digital clock design (2012-09-03, VHDL, 709KB, 下载7次)
电子表的设计包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块
module clock(clk,rst,clock_en,second,minute,hour)
input clk,rst,clock_en
output[5:0]second,minute,hour
reg[5:0]second,minute,hour
(2012-06-19, VHDL, 109KB, 下载3次)
本数字钟可实现正常计时，支持12小时和24小时两种计时方式的切换，允许用户手动调时和整点报时功能。
系统对外向用户提供了两个按键:功能键和调整键.功能键用于功能选择,调整键用于相关的时间调整. 当接通电源后系统便开始正常计时，如果按一下功能键，则进入调小时模式,再按一次则进入调分模式,再按则进入12/24小时模式选择设定,再按则恢复到正常计时状态. 在正常计时状态下，用户可以选择12或24小时的计时方式，第六个数码管的右下方小点亮表示是12小时模式，不亮表示24小时。整点报时时，六个数码管的小点会同时亮。
当用户通过按键进入校时状态时，第二个数码管的小点变亮，表示现在在对小时进行设置；同样，进行校分状态时，第四个数码管的小点会亮，表示现在正在对分钟进行设置。
The digital clock can achieve normal timing, support for 12 hours and 24 hours two timing mode switch allows the user to manually tune and the whole hour. Systems external to provide users with two keys: the function key and adjust the key function keys for function selection and adjustment button for the relevant time to adjust the power system began timing, if you click a function key, adjust the hour mode, and then once for the tone patterns, and then enter 12/24 hour mode select Settings, and then restored to normal timekeeping. in normal time status, the user can select 12 or 24 hours timing sixth of the way, the bottom right of the small digital tube light 12 hour mode, light 24 hours. The whole point of time when the dot of six digital tube light. Button to enter the school when the second digital tube light, that now the hour set Similarly, when the school sub-state, the fourth digital control points will be bright, said that now are minute set. (2012-05-25, VHDL, 17KB, 下载3次)
基于UP3borad开发板的时钟设计，可校时，设置闹钟等
Clock design based on UP3borad the development board, can the school, set the alarm (2012-05-23, VHDL, 354KB, 下载6次)
基于FPGA的多功能数字钟系统（层次化设计）拓展功能包括：报时、校时校分、6到18点时段控制亮灯
Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
(2012-05-17, VHDL, 560KB, 下载7次)
本设计主要研究基于FPGA的数字钟，要求时间以24小时为一个周期,显示年、月、日、时、分、秒。具有校时以及报时功能，可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间。
This design is the main research based on FPGA digital clock, required time to 24 hours for a cycle, display date and time, minutes and seconds. The strike has and function, can to year, month, day, and minutes and seconds to the separate proofreading (2012-03-18, VHDL, 157KB, 下载4次)
基于FPGA的数字时钟，能校时、校分，整点报时。
fpga clock (2012-03-02, VHDL, 316KB, 下载12次)
verilog写的时钟程序，带有校时和闹铃功能
clock program written with verilog (2012-02-25, VHDL, 2KB, 下载7次)
数字钟的电路图.1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能，可以对小时和分单独校时，对分校时的时候，停止分向小时进位。校时时钟源可以手动输入或借用电路中的时钟。4. 具有正点报时功能，正点前10秒开始，蜂鸣器1秒响1秒停地响5次。
Digital clock circuit diagram (2012-02-21, VHDL, 943KB, 下载5次)
多功能数字钟 24小时计时 整点报时功能 闹钟设置功能 校时 复位等
Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc (2012-01-05, VHDL, 2KB, 下载6次)
多功能数字钟 24小时计时 整点报时功能 闹钟设置功能 校时 复位等
Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc (2012-01-05, VHDL, 11KB, 下载7次)
数字时钟，整点报时，有校分校时功能，底层用VHDL，顶层原理图
Digital clock, the whole point of time, when a school campus functions, the bottom with VHDL, top-level schematic (2012-01-05, VHDL, 4KB, 下载4次)
基于VHDL基于VHDL数字电子钟设计（时、分、秒），有校时，分频，倒计时流水灯灯功能。
Based on VHDL VHDL-based design of digital electronic clock (hours, minutes, seconds), there is the school, the frequency, the countdown water lights lamp function. (2012-01-04, VHDL, 2KB, 下载3次)
满足数字钟的一切功能，包括定时，整点报时，时分秒的校时，年月的显示
Digital clock to meet all of the features, including timing, the whole point of time, when every minute of school, the years of the show (2011-12-18, VHDL, 265KB, 下载3次)
电子表的设计,包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块。
Electronic form design, including the normal timing module, LED display module, timing alarm module, timing modules, stopwatch modules. (2011-12-14, VHDL, 2KB, 下载7次)
此数字钟具有时，分，秒计时并显示功能；
2.能进行24/12小时制计时模块的切换；
3.具有校时，清除功能，能对时，分，秒进行调整；
4.具有整点报时功能：在59分51秒，59分53秒，59分55秒，59分57秒发出低音256HZ信号，在59分59秒发出一次高音1024HZ信号，音响持续一秒钟，在1024HZ音响结束时刻即为整点；
This digital clock with hours, minutes, seconds, chronograph and display 2 24/12 hour time capable of switching modules 3 with the school, clean up, can the hours, minutes, seconds to adjust 4 with The whole point timekeeping functions: in 59 minutes and 51 seconds, 59 minutes and 53 seconds, 59 minutes and 55 seconds, 59 minutes and 57 seconds bass 256HZ signal sent in 59 minutes and 59 seconds to issue a treble 1024HZ signals, sound for one second, sound in 1024HZ end time is the whole point (2011-11-13, VHDL, 703KB, 下载4次)
多功能数字钟，实现了计时、校分、闹钟、日历等功能，已通过仿真验证
Multifunction digital clock, to achieve the timing, the school points, alarm clock, calendar and other functions, has been verified by simulation (2011-09-23, VHDL, 1251KB, 下载10次)
实现超多功能数字钟的vhdl硬件实现，可以实现校时校分闹铃，多模切换，多模同时工作
Ultra-versatile digital clock vhdl hardware implementation can be achieved when the school hours the school alarm, multi-mode switching, multi-mode simultaneously (2011-08-03, VHDL, 519KB, 下载4次)
1.计时功能：包括时、分、秒的计时
2.定时与闹钟功能：能在设定的时间按发出闹铃声
3.校时功能：对小时、分钟和秒能手动调整以校准时间
4.整点报时功能
5.利用数码管显示时间
1. The timer function: including, minutes and seconds when the timing
2. The timing and alarm clock function: set time out according to the alarm
3. When the function of hours, minutes and: can manual adjustments to calibration second time
4. Strike on the function
5. Using digital pipe display time (2011-07-29, VHDL, 2KB, 下载4次)