UFSC语言和硬件描述课程知识库，Araranguá校区。，
Repository for the Language and Hardware Description course at UFSC, Araranguá campus., (2023-03-02, VHDL, 0KB, 下载0次)
在quarters ii上连接alter公司开发板实现的数字钟，可以手动校时校分。
Connect the digital clock implemented by alter development board on quarters ii, and it can proofread the time manually. (2019-04-10, VHDL, 2980KB, 下载0次)
基于VHDL的数字时钟课程设计，可实现校时、计时已经闹钟功能。
The course design of digital clock based on VHDL can realize the alarm clock function of school hour and time. (2018-12-25, VHDL, 186KB, 下载5次)
（1）正常计时：秒（60）、分（60）、小时（24）计数；秒计时的频率为1Hz，数码管用动态扫描实时显示计时的小时、分、秒。
（２）整点报时：逢整点蜂鸣器在“59”分钟的第51、53、55、57秒发频率为500Hz的低音，在“59”分钟的第59秒发频率为1000Hz的高音。
（３）校时：
校小时, 显示小时数码管以4Hz的频率递增计数；
校分, 显示分数码管以4Hz的频率递增计数；
校秒, 秒清0。
(1) normal time: second (60), sub (60), hour (24) count; the frequency of second time is 1Hz, the digital tube dynamic scan real-time display time, minute, second.
(2) whole point: a buzzer with a frequency of 500Hz in fifty-first, fifty-third, fifty-fifth and 57 seconds of the "59" minute, and the frequency of 1000Hz in the fifty-ninth seconds of "59" minutes.
(3) school:
The hour is displayed, and the number of the hour digital tube is increased with the frequency of 4Hz.
The score is displayed, and the digit tube is increased by counting the frequency of 4Hz.
School seconds, second clear 0. (2018-07-04, VHDL, 46KB, 下载0次)
用FPGA实现闹钟，校时，计时功能，基于quartus II
Realization of alarm clock, school time, time function (2018-05-12, VHDL, 4189KB, 下载0次)
基于verilog简单数字时钟程序，可实现校时，校分功能
Based verilog simple digital clock procedures, can be achieved when the school, school division function (2016-07-03, VHDL, 1128KB, 下载1次)
基于FPGA的数字万年历设计。可显示年月日时分秒星期，可校时，可整点报时。
FPGA-based design of digital calendar. Displays the date when the minutes and seconds the week, when the school can be the whole point timekeeping. (2016-06-27, VHDL, 150KB, 下载8次)
数字时钟，实现24小时数码管显示，可以实现按键校时
Digital clock, 24 hours to achieve digital display, you can achieve the key school (2016-06-17, VHDL, 1789KB, 下载2次)
数字钟；可以实现校时、走时、单独计时以及闹钟功能。
Digital clock can be achieved when the school, while walking alone timekeeping and alarm function. (2016-05-21, VHDL, 432KB, 下载2次)
该程序主要是用Verilog HDL语言编写的多功能数字钟，包括校时，调试，整点报时和万年历模块。
The program is mainly used Verilog HDL language multifunction digital clock, including at school, debugging, the whole point timekeeping and calendar modules. (2016-05-14, VHDL, 9KB, 下载5次)
显示时、分、秒，有手动校时功能，计时过程具有报时功能
Display hours, minutes, seconds, manual timing function, timing processes with chime (2016-03-26, VHDL, 13KB, 下载1次)
信号定义： clk： 标准时钟信号，本例中，其频率为4Hz； clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz； mode： 功能控制信号； 为0：计时功能； 为1：闹钟功能； 为2：手动校时功能； turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟； 若长时间按住该键，还可使秒信号清零，用于精确调时； change： 接按键，手动调整时，每按一次，计数器加1； 如果长按，则连续快速加1，用于快速调时和定时； hour,min,sec：此三信号分别输出并显示时、分、秒信号， 皆采用BCD码计数，分别驱动6个数码管显示时间； alert： 输出到扬声器的信号，用于产生闹铃音和报时音； 闹铃音为持续20秒的急促的“嘀嘀嘀”音，若按住“change”键， 则可屏蔽该音；整点报时音为“嘀嘀嘀嘀—嘟”四短一长音； LD_alert： 接发光二极管，指示是否设置了闹钟功能； LD_hour： 接发光二极管，指示当前调整的是小时信号； LD_min： 接发光二极管，指示当前调整的是分钟信号。
Signal definition: clk: standard clock signal, in this case, the frequency of 4Hz clk_1k: generating an alarm sound, the sound of the chime of the clock signal, in this case a frequency of 1024Hz mode: function control signal to 0: timing functions 1: alarm clock function 2: Manual calibration function turn: take the keys, function in the manual when school choice is to adjust the hours, or minutes if long press the button, but also to second signal cleared for precise time-setting change: access key, manually adjust the time, every time you press, the counter is incremented if long press, then in quick succession by 1, when used to quickly tune and timing hour, min, sec: The three signals are output and display hours, minutes, seconds signal using BCD code are counted separately driven six digital tube display time alert: a signal output to the speaker for generating an alarm tone chime tone alarm tone sustained 20 seconds of rapid " Didi tick" sound, if the hol (2015-12-09, VHDL, 16KB, 下载2次)
这是本人在学校做的一个DDS信号发生器，频率相位可调。输入时钟50Mhz
DDS phase frequency adjustable Verilog (2015-07-29, VHDL, 2380KB, 下载22次)
基于fpga的多功能数字时钟 在数码管显示
verilog语言编写 可实现校时 暂停以及设定闹钟的功能
FPGA time clock (2015-05-02, VHDL, 74KB, 下载4次)
采用可综合的Verilog代码编写一个带闹钟功能的数字钟。使其具有以下功能：
1)计时功能：包括小时、分钟、秒钟。
2)校时功能：对小时、分钟和秒钟进行手动校时。
3)定时和闹钟功能：能在手工设定的时间产生闹铃音。
Using synthesizable Verilog coding a digital clock with alarm. It has the following features:
1) timing functions include: hours, minutes, seconds.
2) When the school functions: hours, minutes and seconds to the manual correction.
3) timing and alarm functions: to produce an alarm sound at the set time manually. (2015-01-24, VHDL, 2KB, 下载8次)
数电实验 设计并实现一个学校作息时间管理系统 有常态、考试和假日三种工作模式，利用点阵显示。可以进行校时.里面包括各分程序和最后的FINAL总程序，以及报告和实验说明。
Number of electric experimental design and implement a school management system has normal schedule, examinations and holidays three operating modes, using the dot display. When can the school. Which includes the sub-program and final FINAL total program, as well as reports and experiments. (2014-12-15, VHDL, 4320KB, 下载3次)
采用 6 个数码管分别显示小时、分钟和秒的数值；
(2) 计时方式可在 12 小时/24 小时之间切换；
(3) 通过按键可以对 “时”和 “分”进行校时，同时秒计数器清零。
Using six digital tube display hours, minutes and seconds values
(2) the timing mode can be between 12 hours/24 hours switch
(3) may be on the when and points in the school through the key, while the second counter is cleared. (2014-12-08, VHDL, 530KB, 下载1次)
这个程序是基于Quartus II的，能通过数码管显示时、分、秒，具有闹钟的功能，能通过按键校时。
his program is based on the Quartus II, and when through digital display hours, minutes, seconds, and has an alarm clock function, button through school. (2014-11-30, VHDL, 1KB, 下载4次)
多功能数字钟，具有调时校时，整点报时，闹铃及其设定等功能，可直接下载到DE0开发板上
verilog clock (2014-10-29, VHDL, 177KB, 下载3次)
可以自动计时与校时的电波钟程序，内含解码程序
Timing and clock radio automatically when the school program, containing decoding program (2014-10-21, VHDL, 723KB, 下载15次)