实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。
关键字：数字钟 闹钟 仿真 准点报时
Quartus II software by means of experimental Lee designed a multi-functional digital clock and realized the school, the school hours, cleared, and the whole point of time keeping and other basic functions, in addition to achieve the alarm clock, week, music, alarm, etc. Additional function. This paper carried out using Quartus II schematic design and simulation debugging, and finally verified in the experimental board design is correct. Keywords: digital clock alarm clock simulation of quasi-point of time (2010-05-08, VHDL, 1158KB, 下载13次)
闹钟、电子钟典型实例，具有校时，整点报时等功能
Alarm clock, electronic clock typical example, a school, the whole point of time and other functions (2010-04-25, VHDL, 245KB, 下载7次)
多功能数字时钟课程设计可用的,含手动校时电路，整点报时电路。报时长短需要自己设置程序
digital clock decode (2010-04-24, VHDL, 1KB, 下载9次)
eda实验时钟电路系统由秒时钟产生电路、走时电路模块、数字显示模块、校时模块、语音报时模块、工业控制模块
eda test clock circuit generated by the second clock circuit, the circuit blocks away, the digital display module, the campus module, voice timekeeping module, industrial control modules (2010-04-18, VHDL, 2578KB, 下载27次)
基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。
FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. (2010-04-07, VHDL, 62KB, 下载27次)
这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。
This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, the whole point timekeeping, alarm clock function. (2010-03-06, VHDL, 773KB, 下载27次)
多功能数字钟实现闹铃，整点报时，校时，仿广播电台报时功能
multifuntional digital clock written in verilog (2010-02-12, VHDL, 1KB, 下载7次)
具有“秒”、“分”、“时”计时功能，小时按24小时制计时。
具有校时功能，能够对“分”和“小时”进行调整。
具有整点报时功能。在59分51秒、53秒、55秒、57秒发出低音512Hz信号，在59分59秒时发出一次高音1024Hz信号，音响持续1秒钟，在1024Hz音响结束时刻为整点。
With "seconds", "minutes", "hour" timing function, hours at a 24-hour clock time. When a school function, be able to "minutes" and "hours" to adjust.With the whole point timekeeping function. In 59 minutes and 51 seconds, 53 seconds, 55 seconds, 57 seconds sent the bass 512Hz signal, in 59 minutes and 59 seconds to issue a Treble 1024Hz signal, Sound for 1 second, at 1024Hz audio end of the time for the whole point. (2010-01-25, VHDL, 330KB, 下载7次)
多功能数字钟，有校时，仿广播报时，整点报时，闹铃等功能！
Multifunction digital clock, there are schools, the fake radio timekeeping, the whole point timekeeping, alarm and other functions! (2010-01-23, VHDL, 1KB, 下载95次)
可实现校时，仿电台报时，闹钟，报整点时数
The school can be realized when the fake radio timekeeping, alarm clock, reported that the number of hours the whole point of (2009-12-30, VHDL, 13KB, 下载18次)
1．能正常计时。显示模式分为24小时制和12小时制。其中12小时制须显示上、下午。“时”、“分”、“秒”都要显示。
2．具有快速校准时、分、秒的功能。手动校准，用一个功能键选择校时、校分功能，用另一功能键调校对应时、分数值。
3．整点自动报时。在离整点10s时，便自动发出鸣叫声，步长1s，每隔1s鸣叫一次，前四响是低音，最后一响为高音，最后一响结束为整点。
1. To resume normal time. Display mode is divided into 24-hour and 12-hour clock. Including 12-hour clock to be displayed on the afternoon. "Time", "sub", "seconds" must be displayed.
2. Fast calibration, minutes and seconds functions. Manual calibration, using a function button to select the school, the school hours functions, corresponding with another function key set, the score values.
3. The whole point of automatic timekeeping. The whole point away from the 10s, they automatically send calls, step 1s, at intervals of 1s tweet once, the first four bass sound is the last one for the treble ring, ring the end of the last one for the whole point. (2009-12-22, VHDL, 155KB, 下载6次)
数字钟 实现闹钟 定时校时 仿电台报时 利用verilog实现的 数电实验代码
alarm clock (2009-12-09, VHDL, 321KB, 下载6次)
s1. 所设计数字钟具有“时”、“分”、“秒”的十进制数字显示（小时从00～23）。
2. 可以进行手动校时、校分功能。
3. 能进行整点报时。从59分51秒开始每隔2秒钟连续发出四次低音“嘟。嘟、嘟、嘟”，，最后一次发出高音“嗒”。此信号响起时即达整点。
you can see see (2009-12-03, VHDL, 157KB, 下载24次)
1、24小时计数显示；
2、具有校时功能（时，分） ；
3、实现闹钟功能（定时，闹响）；
1,24 hours counting display 2, with the school when the function (hour, minute) 3 to achieve alarm functions (timing, downtown ring) (2009-12-01, VHDL, 7KB, 下载4次)
基于vhdl的数字钟,分别由6个数码管显示24小时、60分钟、60秒的计数显示；设有校时、校分、秒清零校正功能，分别由3个按键控制；验证可用。
On vhdl digital clock, respectively, by 6 digital tube display 24 hours, 60 minutes, 60 seconds of the count display with school hours, school hours, seconds, cleared correction function, respectively, by three buttons control verification is available. (2009-11-13, VHDL, 261KB, 下载3次)
多功能数字钟 能进行正常的时、分、秒计时功能, 分别由6个数码管显示24小时、60分钟、60秒钟的计数器显示。
2. 能利用实验系统上的按键实现“校时”“校分”功能：
3. 能利用扬声器做整点报时
VHDL (2009-10-23, VHDL, 1000KB, 下载29次)
实现一个能显示小时、分钟、秒的多功能时钟，具有整点报时、闹钟、手动校时功能。
To achieve a can display hours, minutes, seconds, multi-functional clock, with the whole point timekeeping, alarm clock, manual, when the school functions. (2009-10-08, VHDL, 76KB, 下载2次)
这时一个关于数字钟的VHDL程序，有计时、校时、报时等功能
When a digital clock on the VHDL program, there is time, school time, timer and other functions (2009-09-22, VHDL, 79KB, 下载6次)
这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用
When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design (2009-09-22, VHDL, 1KB, 下载7次)
这时用VHDL语言编写的多功能数字钟，具有正常的计时功能，还能进行校时、校分，并且具有整点报时功能
Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of (2009-09-22, VHDL, 445KB, 下载13次)