这是本人在学校做的一个DDS信号发生器，频率相位可调。输入时钟50Mhz
DDS phase frequency adjustable Verilog (2015-07-29, VHDL, 2380KB, 下载22次)
可以自动计时与校时的电波钟程序，内含解码程序
Timing and clock radio automatically when the school program, containing decoding program (2014-10-21, VHDL, 723KB, 下载15次)
基于GPS的高精度时钟在线校频与授时研究.pdf,算法是基于最小二乘法的，同步精度达到-25-+25ns
Online GPS-based precision clock frequency and timing of the school, the algorithm is based on the least squares method, the synchronization accuracy reaches-25-+25 ns (2013-09-14, VHDL, 894KB, 下载13次)
数字钟verilog程序，实现了校时、闹钟校正、整点报时、当前时间与闹钟时间切换显示功能。
Digital clock verilog program, school, alarm clock correction, the whole point timekeeping function. (2012-12-15, VHDL, 100KB, 下载10次)
基于FPGA的数字时钟，能校时、校分，整点报时。
fpga clock (2012-03-02, VHDL, 316KB, 下载12次)
多功能数字钟，实现了计时、校分、闹钟、日历等功能，已通过仿真验证
Multifunction digital clock, to achieve the timing, the school points, alarm clock, calendar and other functions, has been verified by simulation (2011-09-23, VHDL, 1251KB, 下载10次)
功能要求：
分离模块要求：
1）设计一个可以显示012345的显示电路，并利用单片机实现。
2）利用按键切换，然后显示ABCDEF
3）按键切换的动作，全部用串口进行通信。
设计一个开关，当进行切换后，程序再进入主要要求。
主要要求：
(1) 显示准确的北京时间（时、分、秒），可用24小时制式；
(2) 随时可以调校时间。
(3) 增加公历日期显示功能（年、月、日），年号只显示最后两位；
(4) 随时可以调校年、月、日；
(5) 允许通过转换功能键转换显示时间或日期。
(6) 所有按键需要通过串口自发自收来调校各种功能。
Functional requirements:
Separation module requires:
1) design a display can show 012,345 circuit, which uses single chip.
2) the use of key switching, and then display the ABCDEF
3) button to switch the action, all with the serial communication.
Design of a switch, when to switch, the program re-entering the main requirement.
Key requirements:
(1) shows the exact Beijing (hours, minutes, seconds), available 24 hours format
(2) can be adjusted at any time.
(3) increasing the Gregorian calendar display function (year, month, day), era show only the last two
(4) can always adjust the year, month, day
(5) allows conversion by converting function key display time or date.
(6) All keys need to adjust the serial port of spontaneous self-closing functions. (2011-04-24, VHDL, 10KB, 下载12次)
本文介绍了一个多功能电子钟的设计方案。该方案具有计时、整点报时、校时、校分、闹钟等多项功能。此方案基于Altera 公司的 Cyclone 芯片及Quartus II 7.2 软件。整体设计采用自顶向下的设计思想，大量使用了器件模块化操作。本文对于研究数字钟及扩大其应用，有着非常现实的意义。
This paper describes a multi-clock design. The program has the time, the whole point of time, school hours, school hours, alarm clocks and many other features. This program is based on Altera' s Cyclone chip and Quartus II 7.2 software. The overall design using top-down design, extensive use of modular operation of the device. This digital clock for research and expand its application, has a very practical significance. (2010-09-08, VHDL, 756KB, 下载12次)
实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。
关键字：数字钟 闹钟 仿真 准点报时
Quartus II software by means of experimental Lee designed a multi-functional digital clock and realized the school, the school hours, cleared, and the whole point of time keeping and other basic functions, in addition to achieve the alarm clock, week, music, alarm, etc. Additional function. This paper carried out using Quartus II schematic design and simulation debugging, and finally verified in the experimental board design is correct. Keywords: digital clock alarm clock simulation of quasi-point of time (2010-05-08, VHDL, 1158KB, 下载13次)
多功能数字时钟课程设计可用的,含手动校时电路，整点报时电路。报时长短需要自己设置程序
digital clock decode (2010-04-24, VHDL, 1KB, 下载9次)
eda实验时钟电路系统由秒时钟产生电路、走时电路模块、数字显示模块、校时模块、语音报时模块、工业控制模块
eda test clock circuit generated by the second clock circuit, the circuit blocks away, the digital display module, the campus module, voice timekeeping module, industrial control modules (2010-04-18, VHDL, 2578KB, 下载27次)
基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。
FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. (2010-04-07, VHDL, 62KB, 下载27次)
这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。
This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, the whole point timekeeping, alarm clock function. (2010-03-06, VHDL, 773KB, 下载27次)
可实现校时，仿电台报时，闹钟，报整点时数
The school can be realized when the fake radio timekeeping, alarm clock, reported that the number of hours the whole point of (2009-12-30, VHDL, 13KB, 下载18次)
s1. 所设计数字钟具有“时”、“分”、“秒”的十进制数字显示（小时从00～23）。
2. 可以进行手动校时、校分功能。
3. 能进行整点报时。从59分51秒开始每隔2秒钟连续发出四次低音“嘟。嘟、嘟、嘟”，，最后一次发出高音“嗒”。此信号响起时即达整点。
you can see see (2009-12-03, VHDL, 157KB, 下载24次)
这时用VHDL语言编写的多功能数字钟，具有正常的计时功能，还能进行校时、校分，并且具有整点报时功能
Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of (2009-09-22, VHDL, 445KB, 下载13次)
以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。
VHDL language before learning to do procedures in an electronic alarm clock, you can realize hours, minutes and seconds of time and from time to time, school time, alarm clock, the whole point timekeeping function. (2008-09-25, VHDL, 166KB, 下载13次)
基于bcd码校时的数字钟，带闹钟，正点报时，和日历功能
Price coverlet bcd tungsten cavity时corchorifolius tub callous钟turbulent age钟， ， ，时forlorn Hao Yu Rui Kun Dang 日 Xikui (2008-07-11, VHDL, 2KB, 下载29次)
两个按键控制校时的VHDL时钟源码，带定时闹钟和日历功能
Two buttons control the school at the time of VHDL source clock, alarm clock and calendar with timing function (2008-07-11, VHDL, 2KB, 下载17次)
用VHDL语言编写的一个乘法器校程序
是基于BOOTH算法的
VHDL language using a multiplier BOOTH school program is based on the algorithm (2008-05-22, VHDL, 1KB, 下载25次)