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按分类查找All VHDL/FPGA/Verilog(110) 

[VHDL/FPGA/Verilog] fpga-sound-effects

在Arty A7 FPGA上开发的音效项目。
Sound Effects Project developed on Arty A7 FPGA. (2024-02-27, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1709201097261069.html

[VHDL/FPGA/Verilog] fpga-projects

Arty A7-35T FPGA的实验
Experiments with an Arty A7-35T FPGA (2024-02-04, Tcl, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1707048374463296.html

[VHDL/FPGA/Verilog] SoomRV-Arty

Arty A7 100T FPGA开发板上的SoomRV
SoomRV on the Arty A7 100T FPGA dev board (2023-11-22, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1700921683436932.html

[VHDL/FPGA/Verilog] AES_proto

本项目参考[http:zongyue.top:8090存档aes%E5%92%8Csm4s%E7%9B%92%E5%A4%8D%E5%90%88%E5%9F%E5%AE%9E7%8E%B0%E6%96...]9E%E7%8E%B0%E6%96%B9%E6%B3%95),
This project is referred to http://zongyue.top:8090/archives/aes%E5%92%8Csm4s%E7%9B%92%E5%A4%8D%E5%90%88%E5%9F%9F%E5%AE%9E%E7%8E%B0%E6%96%B9%E6%B3%95 AES verilog exercises made for the basics of S-box generation (2023-10-21, Others, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1697872146638813.html

[VHDL/FPGA/Verilog] NexysLib

RISC-V的Nexys A7驱动程序
Nexys A7 drivers for RISC-V (2022-08-17, C, 1036KB, 下载0次)

http://www.pudn.com/Download/item/id/1660712471277991.html

[VHDL/FPGA/Verilog] Mimas-A7

Mimas A7–Artix 7 FPGA开发板<https://numato.com产品Mimas-A7-Artix-7-FPGA-Development-Board>
Mimas A7–Artix 7 FPGA开发板<https://numato.com产品Mimas-A7-Artix-7-FPGA-Development-Board> (2023-02-07, C, 22268KB, 下载0次)

http://www.pudn.com/Download/item/id/1675734305524134.html

[VHDL/FPGA/Verilog] cmod-a7-35t_leon3

GRLIB GPL支持Digilent CMOD A7 35T板
GRLIB GPL support for Digilent CMOD A7 35T board (2020-01-05, VHDL, 2651KB, 下载0次)

http://www.pudn.com/Download/item/id/1578210787694551.html

[VHDL/FPGA/Verilog] Nexys-A7-myKeyBoard

用于将键盘连接到Nexys A7并实现简单计算器的verilog代码
verilog code for connecting keyboard to Nexys A7 and implementing a simple calculator (2019-12-06, HTML, 4583KB, 下载0次)

http://www.pudn.com/Download/item/id/1575605098763804.html

[VHDL/FPGA/Verilog] verilog

FPGA Nexys A7板的Verilog代码
Verilog code for FPGA Nexys A7 Board (2022-05-26, HTML, 11988KB, 下载0次)

http://www.pudn.com/Download/item/id/1653510939167099.html

[VHDL/FPGA/Verilog] TFT_PIC_e6

128×160规格TFT显示屏显示图片的源代码
128 x 160 specifications TFT display picture of the source code (2018-08-18, Verilog, 6586KB, 下载3次)

http://www.pudn.com/Download/item/id/1534587606175515.html

[VHDL/FPGA/Verilog] FpgaMskMod

基于verilog编写的MSK调制程序,modsim仿真波形正确
Verilog based MSK modulation program written, modsim simulation waveform correct (2018-04-26, Verilog, 1059KB, 下载26次)

http://www.pudn.com/Download/item/id/1524720328537813.html

[VHDL/FPGA/Verilog] DDR3_A4

xilinx FPGA A7 驱动DDR3的DEMO例程
DEMO routines driven by Xilinx FPGA A7 for DDR3 (2018-04-13, Verilog, 23789KB, 下载14次)

http://www.pudn.com/Download/item/id/1523619154243870.html

[VHDL/FPGA/Verilog] UART_E6

用于测试FPGA串口接收,带singelTap。便于观测。
Used to test the FPGA serial port reception, with singelTap. Convenient observation. (2017-07-28, Verilog, 6463KB, 下载1次)

http://www.pudn.com/Download/item/id/1501248970691648.html

[VHDL/FPGA/Verilog] Ali3328F-A1

Original m3328f a1 firmware
Original m3328f a1 firmware (2013-10-15, Windows_Unix, 283KB, 下载5次)

http://www.pudn.com/Download/item/id/2374425.html

[VHDL/FPGA/Verilog] mlt

--a0 a1 的输入我们用 k1 k2 代替 --b0 b1 的输入我们用 k3 k4 代替 --一开始数码管显示的是9.应为(11)*(11)就等于9 --数码管显示相减结?
- A0 a1 input we use the k1 k2 instead- b0 b1 input with k3 k4 instead- a digital display is 9. (11)* (11) is equivalent to 9- digital display subtracting the knot? (2013-04-03, VHDL, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/2184599.html

[VHDL/FPGA/Verilog] sub

--a0 a1 a2的输入我们用 k1 k2 k3 代替 --b0 b1 b2的输入我们用拨码开关代替。 --b0用拨码开关1输入,BMK1用杜邦线接24脚 --b1用拨码开关2输入,BMK2用杜邦线接25脚 --b2用拨码开关3输入,BMK3用杜邦线接26脚 --一开始数码管显示的是0.应为111-111就等于0 --数码管显示相减结果
- A0 a1 a2 input we use k1 k2 k3 instead the- b0 b1 b2 input, we use DIP switches instead.- B0 DIP switch input, BMK1 with DuPont line by 24 feet- b1 DIP switch 2 input, BMK2 with DuPont line by 25 feet- b2 DIP switch 3 input, BMK3 connected with DuPont line 26 feet- a digital display of 0 is equivalent to 111-111 0- digital display subtraction results (2013-04-03, VHDL, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/2184597.html

[VHDL/FPGA/Verilog] add

--a0 a1 a2的输入我们用 k1 k2 k3 代替 --b0 b1 b2的输入我们用拨码开关代替。 --b0用拨码开关1输入,BMK1用杜邦线接24脚 --b1用拨码开关2输入,BMK2用杜邦线接25脚 --b2用拨码开关3输入,BMK3用杜邦线接26脚 --所以一开始数码管显示的是E.应为111加111就等于E(14) --数码管显示相加结果
- A0 a1 a2 input we use k1 k2 k3 instead the- b0 b1 b2 input, we use DIP switches instead.- B0 DIP switch input, BMK1 with DuPont line by 24 feet- b1 DIP switch 2 input, BMK2 with DuPont line by 25 feet- b2 DIP switch 3 input, BMK3 connected with DuPont line 26 feet- beginning digital tube display E. should be 111 plus 111 is equal to E (14)- Digital tube display result of the addition (2013-04-03, VHDL, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/2184596.html

[VHDL/FPGA/Verilog] add_led

利用K1,K2来代替A2 A1 的数据输入。 利用K3,K4来代替B2 B1 的数据输入。 我把A0和B0都设置成1了。 所以一开始数码管显示的是E.应为111加111就等于E 数码管显示相加结果
K1, K2 to replace A2 A1 data input. K3, K4 to replace B2 B1 data input. A0 and B0 are set to 1. So beginning digital display E. should be 111 plus 111 is equal to the sum of the results of E digital display (2012-09-29, VHDL, 319KB, 下载3次)

http://www.pudn.com/Download/item/id/2004464.html

[VHDL/FPGA/Verilog] VHDL1

4位并行加法器,a3,a2,a1,a0,b3,b2,b1,b0,cin为输入,cout,s3,s2,s1,s0为输出
4-bit parallel adder, a3, a2, a1, a0, b3, b2, b1, b0, cin as the input, cout, s3, s2, s1, s0 as the output (2010-07-13, VHDL, 1KB, 下载3次)

http://www.pudn.com/Download/item/id/1240472.html

[VHDL/FPGA/Verilog] SN7485

his design is a comparator that compares consecutive bits a0...a3 with b0...b3
his design is a comparator that compares consecutive bits a0...a3 with b0...b3 (2009-04-08, VHDL, 45KB, 下载2次)

http://www.pudn.com/Download/item/id/706072.html
总计:110