该代码来自VHDL项目，将NEXYS A7编程为比较器。
This code is from VHDL project the programs a NEXYS A7 to operate as a comparator. (2024-03-21, Others, 0KB, 下载0次)
该代码来自VHDL，将NEXYS A7编程为使用解码器和多路复用器的寄存器
This code is from VHDL project the programs a NEXYS A7 to operate as a register that utilizes a decoder and a multiplexer (2024-03-21, VHDL, 0KB, 下载0次)
在Nexys A7 FPGA板上使用VHDL设计并实现了智能停车系统。
Design and implement a smart parking system using VHDL on the Nexys A7 FPGA board. (2024-03-21, VHDL, 0KB, 下载0次)
存储NEXYS A7（包括微处理器）的所有代码的存储库。主要在VHDL中。
Repository that holds all code for NEXYS A7, including for the microprocessor. Mostly in VHDL. (2024-03-09, VHDL, 0KB, 下载0次)
使用Nexy-A7 100T开发板的UTCN计算机架构实验室的起始代码+文档
Starter code + documentation for the UTCN Computer Architectures laboratories with the Nexy-A7 100T development board (2024-03-06, Others, 0KB, 下载0次)
在Arty A7 FPGA上开发的音效项目。
Sound Effects Project developed on Arty A7 FPGA. (2024-02-27, VHDL, 0KB, 下载0次)
通用图书馆与某工程
general library and some project (2024-02-05, Tcl, 0KB, 下载0次)
Arty A7-35T FPGA的实验
Experiments with an Arty A7-35T FPGA (2024-02-04, Tcl, 0KB, 下载0次)
秒表24小时，Vivado 2023.1——小时、分钟、秒——Nexys A7:ECE课程推荐的FPGA培训板。成员：F…
Stopwatch-24-Hour with Vivado 2023.1 -- Hour, minutes, seconds -- Nexys A7: FPGA Trainer Board Recommended for ECE Curriculum. Member : F… (2024-01-24, Tcl, 0KB, 下载0次)
Nexys A7 FPGA上可编程卵形定时器的Verilog代码
Verilog code for a programmable egg timer on an Nexys A7 FPGA (2024-01-20, Others, 0KB, 下载0次)
C++和Verilog中的8位ALU模拟器，在NEXYS A7 FPGA上实现
8-Bit ALU Simulator in C++ and Verilog, implemented on a NEXYS A7 FPGA (2024-01-18, Others, 0KB, 下载0次)
一个带有M.2 M-Key接口的usb3.0 artix-7 FPGA卡，支持pcileech和riffa等。。。
A pice to usb3.0 artix-7 FPGA card with M.2 M-Key interface, support pcileech and riffa and etc... (2024-01-14, Others, 0KB, 下载0次)
布尔诺理工大学VHDL课程
VHDL course at Brno University of Technology (2024-01-06, VHDL, 0KB, 下载0次)
用verilog编写的Led RGB驱动程序，用于Mimas A7 Mini FPGA开发板
Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board (2024-01-01, Tcl, 0KB, 下载0次)
Arty A7 100T FPGA开发板上的SoomRV
SoomRV on the Arty A7 100T FPGA dev board (2023-11-22, VHDL, 0KB, 下载0次)
针对Arty A7-100T FPGA板的光滑并行SHA-1哈希饼干。
A sleek parallel SHA-1 hash cracker aimed at the Arty A7-100T FPGA board. (2023-11-10, Others, 0KB, 下载0次)
本项目参考[http:zongyue.top:8090存档aes%E5%92%8Csm4s%E7%9B%92%E5%A4%8D%E5%90%88%E5%9F%E5%AE%9E7%8E%B0%E6%96...]9E%E7%8E%B0%E6%96%B9%E6%B3%95），
This project is referred to http://zongyue.top:8090/archives/aes%E5%92%8Csm4s%E7%9B%92%E5%A4%8D%E5%90%88%E5%9F%9F%E5%AE%9E%E7%8E%B0%E6%96%B9%E6%B3%95 AES verilog exercises made for the basics of S-box generation (2023-10-21, Others, 0KB, 下载0次)
SC OBC（SC-OBC-A1）FPGA技术参考手册，
SC OBC (SC-OBC-A1) FPGA Technical Reference Manual, (2023-09-12, CSS, 0KB, 下载0次)
这是Vivado和Artx A7中2048的System Verilog实现，
This is a System Verilog implementation of 2048 in Vivado and Artx A7, (2023-09-08, SystemVerilog, 0KB, 下载0次)
这是我使用Digilent.的ARTY A7 35T开发板实现的采样器。，
This is my implementation of a Sampler using the ARTY A7 35T developement board by Digilent., (2022-04-15, VHDL, 0KB, 下载0次)