之前上载了一个串口接收模块，确实漏了一个文件，这次重新发一下。修改了PARITY_CHECK模块，这样可以支持无校验的应用。这个串口接收模块可以使用parameter参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。
I had uploaded a serial port receiving module, but a file was indeed missed. This time, I will send it again. Modified PARITY_ Check module, which can support the application without parity. The serial port receiving module can use parameter to configure the transmission rate, transmission bit width and verification. Using Verilog voice programming. Users can configure parameters according to the requirements of serial port, and configure FIFO according to the size of buffer. The frame error (stop bit is not high), check error and read FIFO timeout (when FIFO is full, there is new data to) are checked. (2020-05-23, Verilog, 4KB, 下载4次)
本教程的目的是想通过对数字信号处理、计算(Computing) 、算法和数据结构、编程语言
和程序、体系结构和硬线逻辑等基本概念的介绍，了解算法与硬线逻辑之间的关系，从而引入利用Verilog HDL 硬件描述语言设计复杂的数字逻辑系统的概念和方法。
The purpose of this course is to introduce digital signal processing, computing, algorithms and data structures, programming languages.
With the introduction of basic concepts such as program, architecture and hard-line logic, we can understand the relationship between algorithm and hard-line logic, and then introduce the concept and method of designing complex digital logic system using Verilog HDL hardware description language. (2018-11-03, Verilog, 19954KB, 下载7次)
该代码实现了一个基于Wishbone总线协议的DMA控制器，由于SOC可集成的模块越来越多，本文设计的DMAC包含了31个可编程的DMA通道，能够处理多个DMA传输请求。由于数据在Wishbone总线上传输，在总线接口方面，本文设计的DMAC提供了两个既可以作为主机接口又可以作为从机接口的Wishbone接口。当有多个外设同时发出DMA请求时，本文设计的DMAC采用循环优先级和动态优先级相结合的方式，实现了通道仲裁器二级仲裁的功能。为了提高传输效率，本文设计的DMAC不仅支持数据块的传输，还支持高效的分散/集中DMA传输方式。
In this thesis, after in-depth understanding of Wishbone bus protocol and DMA technology, present a design concept of a DMAC integrated into a Wishbone bus based SOC. The DMAC designed in this thesis contains thirty-one programmable DMA channels, which can handle multiple DMA transfer request. As the data is transmitted over the Wishbone bus, the DMAC provides two Wishbone interfaces that can act as a host interface or as a slave interface. When several peripherals issue DMA transfer request at the same time, the DMAC adopts the combination of cyclic priority and dynamic priority to realize the secondary arbitration function of channel arbiter. In order to improve the transmission efficiency, the DMAC not only supports the transmission of data blocks, but also supports efficient scatter/gather DMA transfer mode. (2018-05-28, Verilog, 73KB, 下载7次)
1、PC和寄存器组使用时钟触发。
2、指令存储器和数据存储器存储单元宽度一律使用8位，即一个字节的存储单位。
3、控制器部分可以考虑用控制信号真值表方法（有共性部分）与用case语句方法逐个产生各指令其它控制信号相配合，注意：信号必须与状态配合。。当然，还可以用其它方法，自己考虑。
4、试用的汇编程序，而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况：“小于”和“大于等于”；beq、bne指令必须检查两种情况：“等”和“不等”。这段汇编程序必须尽量优化，同时，给出每条指令在内存中的地址。
1, PC and register groups are clocked.
2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit.
3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own.
4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory. (2017-10-19, Verilog, 6KB, 下载2次)
一些对初学者比较实用的源码，ASK，PSK，FSK调制解调
Some of the more practical source code for beginners (2017-10-15, Verilog, 1251KB, 下载52次)
串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。
UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data width and parity. Using Verilog. The user configured the parameters according to the serial port and configured FIFO according to the size of the buffer. The frame error (stop bit is not high), check errors, and read FIFO timeout (when FIFO is full,and new data come) and so on are examined. (2017-07-21, Verilog, 4KB, 下载14次)