添加了额外的信号来控制来自用户端的序列，并具有加载功能。请首先参考可编程序列检测器。
Added extra signal to control sequence from user end with load functionality. Please refer Programmable Sequence Detector first. (2024-03-29, Verilog, 0KB, 下载0次)
在Basys 3 Artix-7 FPGA训练板上利用Verilog编程为CSE 100 Logic Design类完成的实验室工作
Lab work done for CSE 100 Logic Design class utilizing Verilog programing on a Basys 3 Artix-7 FPGA Trainer Board (2024-01-18, Verilog, 0KB, 下载0次)
在这个项目中，使用Verilog开发了一个复杂的交通灯控制器，并在FPGA（现场可编程...
In this Project, a sophisticated traffic light controller was developed using Verilog and was implemented on an FPGA (Field-Programmable Gate Array) platform. The primary aim was to simulate a realistic traffic management system, employing a Moore state machine design paradigm. (2023-12-08, Verilog, 0KB, 下载0次)
使用通用仪器的AY-3-8913 3语音可编程声音发生器（PSG）芯片提交TinyTapeout，
TinyTapeout submission with the AY-3-8913 a 3-voice programmable sound generator (PSG) chip from General Instruments, (2023-10-03, Verilog, 0KB, 下载0次)
MipSim是使用Flutter desktop for linux的Mips处理器管道的汇编程序。它是计算机组织的项目（第三计算机工程...，
MipSim is assembler for Mips processor pipeline using Flutter desktop for linux. It s project in computer organization (3rd Computer Engineering). (2019-11-23, Verilog, 0KB, 下载0次)
VHDL（Verilog硬件描述语言）是一种可以用来模拟硬件电路的编程语言
VHDL(Verilog Hardware Description Language) is a programming language using which one can simulate hardware circuits (2020-07-30, Verilog, 99KB, 下载0次)
学习vcs的一些有用的资料，包括代码和vcs和uvm的用户指南。
Some useful information for learning VCS, including the code and user guide for VCS and UVM. (2020-08-05, Verilog, 9086KB, 下载7次)
FPGA(现场可编程门阵列)与 CPLD(复杂可编程逻辑器件)都是可编程逻辑器件，它们是在PAL,GAL等逻辑器件的基础之上发展起来的。同以往的PAL,GAL等相比较，FPGA／CPLD的规模比较大，它可以替代几十甚至几千块通用IC芯片。这样的FPGA／CPLD实际上就是一个子系统部件。
本次EDA课程设计就是利用VerilogHDL来设计设计一个2选1多路选择器
FPGA (field programmable gate array) and CPLD (complex programmable logic device) are programmable logic devices. They are developed on the basis of pal, gal and other logic devices. Compared with pal and gal, FPGA / CPLD has a large scale and can replace dozens or even thousands of general IC chips. Such FPGA / CPLD is actually a subsystem component.
This EDA course design is to use Verilog HDL to design a 2-out-of-1 multiplexer (2020-05-11, Verilog, 1KB, 下载0次)
一位加法器，实现两个一位二进制的相加，有进位输入，输出，很好用，自己写的第一个
One bit adder, which can add two bits and one bit binary. It has carry input and output. It is easy to use. The first one written by oneself (2020-04-04, Verilog, 1KB, 下载0次)
verilog编程实现对高速AD芯片AD9280和高速DA芯片AD9708的驱动控制
Verilog programming realizes the drive control of high speed AD chip ad9280 and high speed Da chip ad9708 (2020-03-08, Verilog, 5570KB, 下载2次)
实现Verilog编程，实现超声波测距模块实现测距功能，并将测得的距离显示在数码管上
Verilog programming is realized, ultrasonic ranging module is realized, and the measured distance is displayed on the digital tube (2019-08-10, Verilog, 10705KB, 下载1次)
一个vivado和matalab混合编程的信号发生器，注意要把vivado里面的核文件路径改一下
A signal generator with mixed programming of vivado and matalab, pay attention to changing the path of the core file in vivado (2019-06-18, Verilog, 534KB, 下载6次)
FPGA设计指导和编程设计环境介绍，是FPGA设计很好的参考资料
The design guidance and programming environment of the FPGA are good references for the design of the FPGA. (2019-05-17, Verilog, 2129KB, 下载1次)
FPGA开发全攻略，主要运用Verilog硬件描述语言，进行FPGA编程开发，资料内容丰富详尽
The full strategy of the development of FPGA is mainly based on Verilog Hardware Description Language. The data is rich and detailed. (2019-04-18, Verilog, 26873KB, 下载4次)
upp接口编程资料，实现了UPP接口的双向通信
upp control
reg r_UPP_CH2_START_Sync1;
reg r_UPP_CH2_START_Sync2;
reg r_UPP_CH2_ENABLE_Sync1;
reg r_UPP_CH2_ENABLE_Sync2; (2018-10-11, Verilog, 7KB, 下载4次)
这是一个使用Vivado开发，使用Verilog编程实现，包含testbench和约束文件。
This is a program developed by using Vivado platform. Using Verilog programming, including testbench and constraint files. (2018-05-22, Verilog, 903KB, 下载13次)
用Verilog语言编程实现4位BCD计数器的功能
Write the programm with Verilog language to implement the function of 4 - bit BCD counter. (2018-04-11, Verilog, 25KB, 下载14次)
1.硬件平台： FPGA；
2.编程语言： Verilog；
3.串口通信RS232的Verilog实现版本；
1. hardware platform: FPGA;
2. programming language: Verilog;
The Verilog implementation version of 3. serial port communication RS232; (2018-01-11, Verilog, 55KB, 下载5次)
利用Verilog语言，在PFGA中实现对16位DA芯片AD5761的输出电压进行或編程设置
Using Verilog language, the output voltage of 16 bit DA chip AD5761 is programmed or programmed in PFGA (2017-10-24, Verilog, 1KB, 下载38次)