在这个存储库中，我使用Verilog介绍了一个2级流水线Risc-V处理器的实现，并与它一起构建了一个汇编程序，以使编写程序变得更容易，因此您可以在指令存储器上编写程序并执行它。
In this repository, I introduced an implementation of a 2-stage pipelined Risc-V Processor using Verilog and built an Assembler along with it to make it easier to write programs so you can write them on the instruction memory and execute it. (2024-04-05, Verilog, 0KB, 下载0次)
DE1 SoC现场可编程门阵列（FPGA）的测试台，用于检测DEVCOM陆军研究实验室实施保护技术后系统性能的任何变化
A testbench for the DE1-SoC Field Programmable Gate Array (FPGA) to detect any changes in performance of the system after implementation of protection technology by DEVCOM Army Research Lab (2024-03-09, Verilog, 0KB, 下载0次)
欢迎来到#50DaysVerilogWithMeGitHub存储库，在那里我们开始了一次为期50天的Verilog编程全面旅程。该计划旨在为参与者提供Verilog（一种广泛用于数字设计的硬件描述语言）的结构化增量学习体验。
Welcome to the #50DaysVerilogWithMe GitHub repository, where we embark on a comprehensive 50-day journey into Verilog programming. This initiative is designed to provide participants with a structured and incremental learning experience in Verilog, a hardware description language widely used in digital design. (2024-02-04, Verilog, 0KB, 下载0次)
在本项目中，使用Verilog开发了一种复杂的交通灯控制器，并在FPGA（现场可编程门阵列）平台上实现。主要目标是使用摩尔状态机设计范例模拟真实的交通管理系统。
In this Project, a sophisticated traffic light controller was developed using Verilog and was implemented on an FPGA (Field-Programmable Gate Array) platform. The primary aim was to simulate a realistic traffic management system, employing a Moore state machine design paradigm. (2023-12-29, Verilog, 0KB, 下载0次)
本文在现场可编程门阵列（FPGA）上实现了用于脑电信号分析的滤波器和特征提取器。仿真过程是使用使用Verilog的ISim完成的。所有流程都是使用Xilinx ISE Suite 14.7和Quartus prime 17.1 Lite Edition软件实现和设计的。
In this work filter & feature extractor were implemented for analyzing EEG on Field Programmable Gate Array (FPGA). The simulation process was done by using ISim which used Verilog. All processes were implemented and designed by using Xilinx ISE Suite 14.7 & Quartus prime 17.1 Lite Edition software. (2023-12-22, Verilog, 0KB, 下载1次)
该项目旨在逐块设计和编码微处理器，然后在现场可编程门阵列（FPGA）板上运行。...，
This project was aiming to design and code a Microprocessor block by block and then run it on a Field Programmable Gate Array (FPGA) Board. 8-bit Microprocessor was designed which consisted of Arithmetic Logical Unit (ALU) which can do all necessary mathematical operations. Moreover, measures to prevent hazards and problems were kept in mind. (2019-04-30, Verilog, 0KB, 下载0次)
这是一款电脑游戏，具有侧滚滚动式界面，用Verilog编程。一旦烧毁到FPGA板中，它可以是co...，
This is a computer game with a side-scrolling scroll-style interface, programmed in Verilog. Once burned into an FPGA board, it can be connected to a computer screen and keyboard to start an exciting and thrilling gaming experience. (2023-08-10, Verilog, 0KB, 下载0次)
这项工作实现了一种用于执行局部序列比对的动态编程算法。通过并行，它...
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm. (2019-07-04, Verilog, 12947KB, 下载0次)
Home Brew 8位CPU硬件实现，包括Verilog模拟、汇编程序、“C”编译器和此代表...
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. <https://hackaday.io/project/166922-spam-1-8-bit-cpu> (2022-09-09, Verilog, 179722KB, 下载0次)
vivado使用过程中常见问题总结，NFS挂载问题，SDK裸机编程常见问题，sdk能不能设置保存不自动编译。。。
Summary of common problems in the use of vivado, NFS mount problems, SDK bare machine programming common problems, whether the SDK can be set to save not to automatically compile... (2020-10-12, Verilog, 3297KB, 下载0次)
引入了Verilog HDL硬件描述语言介绍了信号处理与硬线逻辑设计的关系，以及有关的基本概念。
In this paper, Verilog HDL hardware description language is introduced to introduce the relationship between signal processing and hardware logic design, as well as the related basic concepts. (2019-10-28, Verilog, 1323KB, 下载4次)
本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失，自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测
The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection (2019-06-18, Verilog, 1486KB, 下载2次)
Verilog数字系统设计教程第二版。夏宇闻著。本书讲述利用硬件描述语言Verilog HDL设计复杂数字系统的方法。
The second edition of Verilog Digital System Design Course. Xia Yu smells. This book describes the method of designing complex digital system by using hardware description language Verilog HDL. (2019-05-30, Verilog, 42975KB, 下载0次)
在 FLASH 读写测试程序中我们需要实现 FLASH 的设备 ID 的读取，Sector 擦除，Page 编程，数据的读取这四大块的功能
In FLASH read and write test program, we need to realize the functions of reading device ID, Sector erase, Page programming and data reading of FLASH. (2019-03-30, Verilog, 1645KB, 下载5次)
可编程数字系统设计的基本流程
设计输入（原理图文件、硬件描述语言文件、网表输入文件、混合输入文件）项目处理（设计文件检查和编译、设计文件分析和综合、器件适配、设置设计约束）设计校验（生成功能网表、功能仿真、适配后的仿真文件、门级时序仿真）器件编程（生成器件编程文件、器件编程）
原理设计输入方式是利用软件提供的各种原理图库，采用画图的方式进行设计输入。这是一种最为简单和直观的输入方式。原理图输入方式的效率比较低，一般只用于小规模系统设计，或用于在顶层拼接各个已设计完成的电路子模块。
Basic Flow of Programmable Digital System Design
Design Input (schematic diagram file, hardware description language file, netlist input file, mixed input file) project processing (checking and compiling design documents, analysis and synthesis of design documents, device adaptation, setting design constraints) design verification (generating functional netlist, function simulation, adapted simulation files, gate-level timing simulation) device programming (generating component programming text) Programming of Components and Devices
Principle design input mode is to use various schematic library provided by the software to design input by drawing. This is the simplest and most intuitive way to input. The input mode of schematic diagram is inefficient. It is usually only used for small-scale system design or for splicing each completed circuit sub-module at the top level. (2018-12-24, Verilog, 6632KB, 下载1次)
用verliog进行编程，用数码管显示0~F16进制数码循环，并显示对应的流水灯样式
Programming with verliog, using the digital tube to display 0~F16 digit digital loop, and display the corresponding stream light style. (2018-07-01, Verilog, 13KB, 下载2次)
adv7123是常用的视频解码器，常常可用fpga编程控制，使其输出ntsc、pal制式，或者vga显示，这里面全是关于这方面的论文，很值得借鉴参考。
Adv7123 is a commonly used video decoder. It can often be controlled by FPGA programming, so that it can output NTSC, PAL format or VGA display, which is all about the papers in this area, so it is worth learning from for reference. (2018-01-20, Verilog, 17111KB, 下载30次)
在开发板EGO1上实现的小鸟游戏，有详细地模块说明，使用vivdao平台实现
Bird board game on the development board EGO1, a detailed module description, the use of vivdao platform (2017-12-13, Verilog, 510KB, 下载47次)
使用Altera FPGA平台，Verilog编程语言，编写步进电机驱动程序，已在开发板上验证；
on altera fpga flatform, use verilog language, driving stepmotor, and test ok. (2017-10-08, Verilog, 300KB, 下载20次)
使用Verilog编程搭建的测试平台，并连接了VGA等外设，使用MIPS汇编编写逻辑完成的躲避球小游戏
Use Verilog programming to build the test platform, and connect the VGA and other peripherals, using MIPS assembly to write logic to complete the dodge ball game (2017-08-03, Verilog, 11848KB, 下载6次)