数字时钟,实现24小时数码管显示,可以实现按键校时
Digital clock, 24 hours to achieve digital display, you can achieve the key school (2016-06-17, VHDL, 1789KB, 下载2次)
数字钟;可以实现校时、走时、单独计时以及闹钟功能。
Digital clock can be achieved when the school, while walking alone timekeeping and alarm function. (2016-05-21, VHDL, 432KB, 下载2次)
可以自动计时与校时的电波钟程序,内含解码程序
Timing and clock radio automatically when the school program, containing decoding program (2014-10-21, VHDL, 723KB, 下载15次)
数字时钟 LCD1602显示 可以校时。
编译环境QUARTUS II 7.2
Digital clock LCD1602 display can be corrected.
Compilation environment QUARTUS II 7.2
(2014-06-27, VHDL, 2107KB, 下载1次)
verilog电子时钟,可以实现复位、计时、校时、闹钟等多种功能。
verilog electronic clock, you can achieve a variety of functions reset, time, school, alarm clock and so on. (2013-12-12, VHDL, 363KB, 下载5次)
数字钟,实现整点报时以及校时功能,烟大数字逻辑课程实验。
Digital clock, realize the whole point timekeeping and school function, smoke large digital logic course experiment. (2013-11-08, VHDL, 496KB, 下载3次)
多功能数字电子表
(1)正常计时:秒(60)、分(60)、小时(24)计数;秒计时的频率为1Hz,数码管用动态扫描实时显示计时的小时、分、秒。
(2)整点报时:逢整点蜂鸣器在“59”分钟的第51、53、55、57秒发频率为512Hz的低音,在“59”分钟的第59秒发频率为1024Hz的高音。
(3)校时:
校小时, 显示小时数码管以4Hz的频率递增计数;
校分, 显示分数码管以4Hz的频率递增计数;
校秒, 秒清0。
其他:
1.晶振为12 MHz
2. 采用CPLD 器件为ALTERA 的EPM7064SL-44
3.采用数码管显示
Multifunction digital electronic watch (1) normal time: second (60), points (60), hours (24) counts second timing frequency of 1Hz, dynamic scanning real-time display of digital works timekeeping hour, minutes and seconds. (2) The whole point timekeeping: Every whole point of the buzzer in the " 59" minutes of 51,53,55,57 second frequency is 512Hz bass made in the " 59" minutes of the first 59 seconds made the treble frequency is 1024Hz . (3) school: school hours, hours of digital tube display frequency of 4Hz counts school hours, the display of digital 4Hz for counting school, seconds cleared. Others: 1. Crystal is 12 MHz 2. Using ALTERA CPLD device as the EPM7064SL-44 3. Using digital display (2013-08-20, VHDL, 503KB, 下载3次)
设计一个多功能数字时钟:时钟显示,手动校时,整点报时,闹钟功能
Clock manually school, the whole point timekeeping, alarm clock function (2013-04-09, VHDL, 360KB, 下载8次)
多功能时钟,具有正常显示,校时,整点报时,闹钟功能。
Multi-function clock, with a normal school, the whole point timekeeping, alarm clock function. (2012-11-26, VHDL, 470KB, 下载5次)
数字时钟,整点报时,有校分校时功能,底层用VHDL,顶层原理图
Digital clock, the whole point of time, when a school campus functions, the bottom with VHDL, top-level schematic (2012-01-05, VHDL, 4KB, 下载4次)
电子表的设计,包括正常计时模块,LED显示模块,定时报警模块,校时模块,秒表模块。
Electronic form design, including the normal timing module, LED display module, timing alarm module, timing modules, stopwatch modules. (2011-12-14, VHDL, 2KB, 下载7次)
数字钟的实现,包括报时,校时,清零,闹钟等功能,内附源文件电路图跟源代码。
This is a digital clock to achieve the VHDL. Using eight digital tube display!- Adjustable alarm can be school. (2011-06-15, VHDL, 90KB, 下载4次)
闹钟、电子钟典型实例,具有校时,整点报时等功能
Alarm clock, electronic clock typical example, a school, the whole point of time and other functions (2010-04-25, VHDL, 245KB, 下载7次)
多功能数字时钟课程设计可用的,含手动校时电路,整点报时电路。报时长短需要自己设置程序
digital clock decode (2010-04-24, VHDL, 1KB, 下载9次)
可实现校时,仿电台报时,闹钟,报整点时数
The school can be realized when the fake radio timekeeping, alarm clock, reported that the number of hours the whole point of (2009-12-30, VHDL, 13KB, 下载18次)
能手动校时,整点报时的时钟,具有闹钟功能,在实验中测试成功
Can manually school, the whole point of clock time, with alarm clock function, in experiments to test the success of (2009-06-01, VHDL, 408KB, 下载2次)
用VHDL实现的完整数字钟代码,时分秒计时、校时、整点仿电台报时。
Used to achieve a complete VHDL code digital clock, accurate time at school, the whole point of imitation time radio. (2009-05-21, VHDL, 288KB, 下载5次)
简易数字钟,包括时间显示时分秒各位的校时接口,输出BCD码
Simple digital clock, including the minutes and seconds time display when your school interface, the output BCD code (2009-01-02, VHDL, 45KB, 下载3次)
自己写的数字闹钟含校时和闹钟设定,闹钟铃声为梁柱歌曲,
Write their own digital clock and alarm clock with school settings, the alarm tone for the column songs, (2008-07-12, VHDL, 7KB, 下载4次)
用VHDL语言编写的一个乘法器校程序
是基于BOOTH算法的
VHDL language using a multiplier BOOTH school program is based on the algorithm (2008-05-22, VHDL, 1KB, 下载25次)