数电实验 设计并实现一个学校作息时间管理系统 有常态、考试和假日三种工作模式，利用点阵显示。可以进行校时.里面包括各分程序和最后的FINAL总程序，以及报告和实验说明。
Number of electric experimental design and implement a school management system has normal schedule, examinations and holidays three operating modes, using the dot display. When can the school. Which includes the sub-program and final FINAL total program, as well as reports and experiments. (2014-12-15, VHDL, 4320KB, 下载3次)
采用 6 个数码管分别显示小时、分钟和秒的数值；
(2) 计时方式可在 12 小时/24 小时之间切换；
(3) 通过按键可以对 “时”和 “分”进行校时，同时秒计数器清零。
Using six digital tube display hours, minutes and seconds values
(2) the timing mode can be between 12 hours/24 hours switch
(3) may be on the when and points in the school through the key, while the second counter is cleared. (2014-12-08, VHDL, 530KB, 下载1次)
1．具有‘时’、‘分’、‘秒’、‘毫秒’的数码管十进制数字显示。
2. 具有手动校时、校分的功能。
3．具有定时与闹钟功能，能在设定的时间使LED灯亮光。
4．能进行整点报时。即从59分50秒起，每隔2秒钟绿色LED灯点亮一次，连续5次，最后一次红色LED灯点亮一次，表明到达整点。
5、具有秒表功能，能显示1 秒，手动停止。
6、具有倒计时功能，显示小时、分钟、秒。
1. With ' when' , ' points' , ' second' , ' ms' digital tube display decimal digits. (2) When a manual school, school of function. 3. With a timer and alarm clock function, can make the LED lights light at a set time. 4. Can carry the whole point timekeeping. Namely, from 59 minutes and 50 seconds, every 2 seconds the green LED lights up once, five consecutive times, the last time the red LED lights up, indicating that reaches the whole point. 5, with a stopwatch function that can display one percent second manually stopped. 6, with a countdown function, display of hours, minutes, seconds. (2014-03-10, VHDL, 2KB, 下载2次)
基于GPS的高精度时钟在线校频与授时研究.pdf,算法是基于最小二乘法的，同步精度达到-25-+25ns
Online GPS-based precision clock frequency and timing of the school, the algorithm is based on the least squares method, the synchronization accuracy reaches-25-+25 ns (2013-09-14, VHDL, 894KB, 下载13次)
基于QuartusII开发环境，Cyclone III开发板的VerilogHDL多功能数字钟程序。可实现24小时计时，手动校时，闹钟，整点报时功能。分频模块在仿真和烧写是需要改变。
QuartusII based development environment, Cyclone III development board VerilogHDL multifunction digital clock procedures. Can achieve 24-hour clock, manual timing, alarm, hourly chime functions. Frequency module in the simulation and programming needs to change. (2013-07-24, VHDL, 1895KB, 下载4次)
(1)设计一个具有‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
(2)具有手动校时、校分的功能。
(3)闹钟功能，能在设定的时间发出提醒（绿色LED灯闪烁）。
(4)能进行整点报时。从59分50秒起，每隔2秒钟绿色LED灯闪一次，连续5次，达到整点时红色LED灯闪一次。
(1) design a ' when' , ' points' , ' s' decimal digital display (hour timer from 00 to 23). (2) having a manual correction, the correction sub functions. (3) The alarm clock function, can send reminders at a set time (green LED flashes). (4) The whole point timekeeping. Starting at 59 minutes and 50 seconds, every 2 seconds the green LED lights flash five times in a row, when the whole point of the red LED lights flash once. (2013-03-27, VHDL, 2KB, 下载3次)
数字钟(for DE2 开发板)
1.‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
2. 手动校时、校分、校秒的功能。
3．定时与闹钟功能，能在设定的时间发出闹铃声。
4．进行整点报时。从59分50秒起，每隔2秒钟发出一次低音“嘟”的信号，连续5次，最后一次发出高音“嘀”的信号，此信号结束即达到整点。
5、一个秒表，最低位1 秒、60秒，手动停止，手动重置。
6、一个倒计时，显示小时、分钟、秒，可设置时间。
Decimal digital display (hour digital clock (for DE2 development board). ' ' , ' Minutes' , ' seconds' timer from 00 to 23). 2 when manually school, the school points School sec functionality. 3. Timer and alarm clock function, the alarm sounds at the set time. 4. The whole point of time. Starting at 59 minutes and 50 seconds, every 2 seconds issued time bass " beep" signal, five times in a row, the last issued a the treble " tick" signal, this signal the end to reach the whole point. 5, a stopwatch, the lowest 1 seconds, 60 seconds, manually stop manually reset. 6, a countdown display hours, minutes, seconds, set the time. (2012-11-11, VHDL, 887KB, 下载77次)
本设计主要研究基于FPGA的数字钟，要求时间以24小时为一个周期,显示年、月、日、时、分、秒。具有校时以及报时功能，可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间。
This design is the main research based on FPGA digital clock, required time to 24 hours for a cycle, display date and time, minutes and seconds. The strike has and function, can to year, month, day, and minutes and seconds to the separate proofreading (2012-03-18, VHDL, 157KB, 下载4次)
1.计时功能：包括时、分、秒的计时
2.定时与闹钟功能：能在设定的时间按发出闹铃声
3.校时功能：对小时、分钟和秒能手动调整以校准时间
4.整点报时功能
5.利用数码管显示时间
1. The timer function: including, minutes and seconds when the timing
2. The timing and alarm clock function: set time out according to the alarm
3. When the function of hours, minutes and: can manual adjustments to calibration second time
4. Strike on the function
5. Using digital pipe display time (2011-07-29, VHDL, 2KB, 下载4次)
用VHDL编写。称为校时闪烁电路。一般的电子表在校时时都会使被校正的时间不停地闪烁。此模块实现了类似的功能。与我的其它8个模块配套构成一个数字钟。
Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised time(for example,hour) to let the user know time revised. This module implements the similar function. It is one of my total 9 modules that are used to design a digital clock. (2011-06-24, VHDL, 140KB, 下载4次)
功能要求：
分离模块要求：
1）设计一个可以显示012345的显示电路，并利用单片机实现。
2）利用按键切换，然后显示ABCDEF
3）按键切换的动作，全部用串口进行通信。
设计一个开关，当进行切换后，程序再进入主要要求。
主要要求：
(1) 显示准确的北京时间（时、分、秒），可用24小时制式；
(2) 随时可以调校时间。
(3) 增加公历日期显示功能（年、月、日），年号只显示最后两位；
(4) 随时可以调校年、月、日；
(5) 允许通过转换功能键转换显示时间或日期。
(6) 所有按键需要通过串口自发自收来调校各种功能。
Functional requirements:
Separation module requires:
1) design a display can show 012,345 circuit, which uses single chip.
2) the use of key switching, and then display the ABCDEF
3) button to switch the action, all with the serial communication.
Design of a switch, when to switch, the program re-entering the main requirement.
Key requirements:
(1) shows the exact Beijing (hours, minutes, seconds), available 24 hours format
(2) can be adjusted at any time.
(3) increasing the Gregorian calendar display function (year, month, day), era show only the last two
(4) can always adjust the year, month, day
(5) allows conversion by converting function key display time or date.
(6) All keys need to adjust the serial port of spontaneous self-closing functions. (2011-04-24, VHDL, 10KB, 下载12次)
应用8031单片机控制的数字时钟上，在设计上采用硬件计数与软件计数相结合的方式，并且定时器T0采用了中断方式，优先级最高。然后通过开关的闭合与关断来控制闹钟的校时，整点报时等功能。
Application of 8031 controlled digital clock, counting in the design of hardware and software using a combination of counts and using the timer interrupt T0, the highest priority. Then closed through the switch to control the clock and off the school, the whole point of time and other functions. (2010-12-14, VHDL, 862KB, 下载1次)
实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。
关键字：数字钟 闹钟 仿真 准点报时
Quartus II software by means of experimental Lee designed a multi-functional digital clock and realized the school, the school hours, cleared, and the whole point of time keeping and other basic functions, in addition to achieve the alarm clock, week, music, alarm, etc. Additional function. This paper carried out using Quartus II schematic design and simulation debugging, and finally verified in the experimental board design is correct. Keywords: digital clock alarm clock simulation of quasi-point of time (2010-05-08, VHDL, 1158KB, 下载13次)
基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。
FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. (2010-04-07, VHDL, 62KB, 下载27次)
1．能正常计时。显示模式分为24小时制和12小时制。其中12小时制须显示上、下午。“时”、“分”、“秒”都要显示。
2．具有快速校准时、分、秒的功能。手动校准，用一个功能键选择校时、校分功能，用另一功能键调校对应时、分数值。
3．整点自动报时。在离整点10s时，便自动发出鸣叫声，步长1s，每隔1s鸣叫一次，前四响是低音，最后一响为高音，最后一响结束为整点。
1. To resume normal time. Display mode is divided into 24-hour and 12-hour clock. Including 12-hour clock to be displayed on the afternoon. "Time", "sub", "seconds" must be displayed.
2. Fast calibration, minutes and seconds functions. Manual calibration, using a function button to select the school, the school hours functions, corresponding with another function key set, the score values.
3. The whole point of automatic timekeeping. The whole point away from the 10s, they automatically send calls, step 1s, at intervals of 1s tweet once, the first four bass sound is the last one for the treble ring, ring the end of the last one for the whole point. (2009-12-22, VHDL, 155KB, 下载6次)
VHDL数字钟设计程序
设计要求
基本要求：
1、24小时计数显示；
2、具有校时功能（时，分） ；
附加要求：
1、实现闹钟功能（定时，闹响）；
VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additional requirements: 1, the realization of an alarm clock function (timing, downtown ring) (2008-12-23, VHDL, 7KB, 下载129次)
电子闹钟
clk： 标准时钟信号，本例中，其频率为4Hz；
clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz；
mode： 功能控制信号； 为0：计时功能；
为1：闹钟功能；
为2：手动校时功能；
turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟；
若长时间按住该键，还可使秒信号清零，用于精确调时；
change： 接按键，手动调整时，每按一次，计数器加1；
如果长按，则连续快速加1，用于快速调时和定时；
hour,min,sec：此三信号分别输出并显示时、分、秒信号，
皆采用BCD 码计数，分别驱动6 个数码管显示时间；
alert： 输出到扬声器的信号，用于产生闹铃音和报时音；
闹铃音为持续20 秒的急促的“嘀嘀嘀”音，若按住“change”键，
则可屏蔽该音；整点报时音为“嘀嘀嘀嘀—嘟”四短一长音；
LD_alert： 接发光二极管，指示是否设置了闹钟功能；
LD_hour： 接发光二极管，指示当前调整的是小时信号；
LD_min： 接发光二极管，指示当前调整的是分钟信号
err (2008-12-08, VHDL, 2KB, 下载34次)
电子时钟 EDA
基本要求：
24小时计数显示；
具有校时功能（时，分）
附加要求
1、秒表功能（复位，计时
Electronic clock EDA basic requirements: a 24-hour count showed with a school function (hours, minutes,) Additional requirement 1, stopwatch functions (reset, clock (2008-09-18, VHDL, 3KB, 下载33次)
ADC0809采样控制电路的实现ADC0809是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中，转换时间约100us。主要控制信号有，START是转换启动信号，高电平有效。ALE是3位通道选择地址（ADDC、ADDB、ADDA）信号的所存信号。当模拟量送至某一输入端（如IN1或IN2），由3位地址信号选择，而地址信号由ALE锁存。
ADC0809频 实 ADC0809CMOS8位A/D 转 片8 模 饪?兀 煽8模 械一 转 校 转 时 约 100us要藕校START 转 藕牛 叩 平效ALE3位 通 选ADDCADDBADDA藕诺藕拧模 某一 耍 IN1IN23位藕选 瘢 藕ALE file (2008-09-04, VHDL, 28KB, 下载38次)
学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字
Learning to use the FPGA to do a few simple encoders, RS (5,3) code is five characters in 5-3 = 2 has two correction words (2008-04-01, VHDL, 969KB, 下载136次)